The use of nanocrystals and carbon nanotubes to form transistors for non-volatile memory are “paradigm shifts” in manufacturing according to Intel Corporation (Santa Clara, CA) inventors Yuegang Zhang, Udayan Ganguly, and Edwin Kan in United States Patent 7,629,639.
The researchers formed a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. The nanotube/nanocrystal transistor further exhibits a large memory window and a single-electron drain current.
Memory manufacturers are currently researching and developing the next generation of memory devices. One such development includes technology designed to replace current volatile and non-volatile memory technologies. Important elements of a successor include compactness, low price, low power operation, non-volatility, high density, fast read and write cycles, and long life.
Current memory technology is predicted to survive into 65 nanometer process generations. This survival is in part based on the successful integration of, for example, exotic storage, source and drain engineering, copper and low dielectric constant materials for the interconnect levels, and high dielectric constant materials for transistor gates. However, there will thereafter exists a need for new memory materials and technology, particularly for non-volatile memory.
As is well known in the art, Flash memory utilizes a floating gate to store charge indicative of a logical "0" or logical "1" memory state. The floating gate is located between a control gate and a substrate, and relies on hot electron injection and Fowler-Nordheim electron tunneling through a thin tunneling oxide between the floating gate and the substrate for charge injection. An electrical potential, usually between 10 and 13 volts, can be applied to the control gate to excite electrons through the tunneling oxide layer into the floating gate where they are thereafter trapped. The trapped electrons provide excess potential in addition to the potential applied at the control gate. Hence the current through the transistor channel in the substrate is a function of both the control gate voltage and the presence/absence of charge in the floating gate.
Current memory technology is predicted to survive into 65 nanometer process generations. This survival is in part based on the successful integration of, for example, exotic storage, source and drain engineering, copper and low dielectric constant materials for the interconnect levels, and high dielectric constant materials for transistor gates. However, there will thereafter exists a need for new memory materials and technology, particularly for non-volatile memory.
As is well known in the art, Flash memory utilizes a floating gate to store charge indicative of a logical "0" or logical "1" memory state. The floating gate is located between a control gate and a substrate, and relies on hot electron injection and Fowler-Nordheim electron tunneling through a thin tunneling oxide between the floating gate and the substrate for charge injection. An electrical potential, usually between 10 and 13 volts, can be applied to the control gate to excite electrons through the tunneling oxide layer into the floating gate where they are thereafter trapped. The trapped electrons provide excess potential in addition to the potential applied at the control gate. Hence the current through the transistor channel in the substrate is a function of both the control gate voltage and the presence/absence of charge in the floating gate.
In other words, the compounded effect of the stored charge and the control gate voltage sets the resistance in the current channel, controlling the current flow through it. A cell sensor (external circuitry) monitors the potential drop across the current channel in the substrate which is controlled by the resistance of the channel to the current flow. If, for example, the resistance through the gate is greater than a set threshold value in Ohms, it has a logical value of "1." If the resistance drops below the threshold, the logical value changes to "0."
The non-volatility of the memory depends on how securely the electrons are trapped in the floating gate. Among other defects, weak spots in the tunneling oxide (in particular as the tunneling oxide thickness decreases) may enable a filament current that will discharge the entire floating gate and render the device useless as a non-volatile memory element as the floating gate will be unable to store charge for any useful duration which leads to product reliability concerns.
Nanocrystals have been introduced as a paradigm to increase tunneling oxide reliability of Flash memory by dividing a monolithic floating gate into a set of discretely spaced floating gates. In the event of a weak spot or defect in the tunneling dielectric, this discreteness allows the discharge of only the floating gate directly over the defect. The rest of the floating gates are unaffected by the defect instead of the catastrophic leakage of all stored charge from a monolithic floating gate.
Another paradigm shift involves the use of carbon nanotubes in electronic applications. In particular, single-walled carbon nanotubes (SWNTs) are nanometer scale cylindrical tubes that are rolled from a single graphene sheet that can either be grown from a carbon source with the help of a catalyst. Nanotubes can have various crystal orientations and diameters which produces a variety of electronic band structures. Thus, SWNT can either metallic or semiconducting. As a semiconductor, a SWNT or multiple SWNTs can replace the semiconductor (e.g., silicon substrate) in a metal oxide semiconductor field effect transistor (MOSFET) structure. Such devices are also called carbon nanotube field effect transistors (CNFETs). However, while the promise of SWNTs in electronics applications theoretically impressive, SWNT-based electronic manufacturability offers significant hurdles to commercial practicability.
Nanocrystals have been introduced as a paradigm to increase tunneling oxide reliability of Flash memory by dividing a monolithic floating gate into a set of discretely spaced floating gates. In the event of a weak spot or defect in the tunneling dielectric, this discreteness allows the discharge of only the floating gate directly over the defect. The rest of the floating gates are unaffected by the defect instead of the catastrophic leakage of all stored charge from a monolithic floating gate.
Another paradigm shift involves the use of carbon nanotubes in electronic applications. In particular, single-walled carbon nanotubes (SWNTs) are nanometer scale cylindrical tubes that are rolled from a single graphene sheet that can either be grown from a carbon source with the help of a catalyst. Nanotubes can have various crystal orientations and diameters which produces a variety of electronic band structures. Thus, SWNT can either metallic or semiconducting. As a semiconductor, a SWNT or multiple SWNTs can replace the semiconductor (e.g., silicon substrate) in a metal oxide semiconductor field effect transistor (MOSFET) structure. Such devices are also called carbon nanotube field effect transistors (CNFETs). However, while the promise of SWNTs in electronics applications theoretically impressive, SWNT-based electronic manufacturability offers significant hurdles to commercial practicability.
FIG. 1: illustration of a substrate cross section of a silicon nanocrystal memory device including 1-dimensional band diagrams for write, store, and erase functions of the silicon nanocrystal memory device
As introduced, carbon nanotubes, and in particular single-walled carbon nanotubes have become increasingly popular for both their mechanical and electrical properties. One approach has been to use the carbon nanotube as the semiconductor for the channel region of the transistor. Carbon nanotubes have increased carrier mobility versus bulk silicon (i.e. higher conductivity normalized to cross sectional area) and further exhibit higher current density than bulk silicon. Further, carbon nanotubes are naturally small and easy to control with an electric field.
Said differently, a carbon nanotube can be compared to a highway with only one lane that can be easily blocked and unblock to control the traffic thereon. This is particularly useful to improve the sensitivity of the channel region of the carbon nanotube nanocrystal memory device of an embodiment and resulting memory window thereof. Further the carbon nanotube, with only one conduction dimension, mitigates the percolation current challenge of the two-dimensional array of the nanocrystals as discussed above.
FIG. 1 illustrates a substrate cross section of a silicon nanocrystal memory device 100 including a gate 101, drain 102, source 103, silicon nanocrystals 104, tunnel oxide 105, current channel 106 in the silicon substrate 108 and control oxide 107. The silicon nanocrystal 104 floating gate (scale increased for illustration only) is located between the control oxide 107 and the tunnel oxide 105, and relies on hot electron injection and Fowler-Nordheim electron tunneling through the thin tunnel oxide 105 to accumulate and disperse charge. An electrical potential, usually between 10 and 13 volts, can be applied to the gate 101 to excite electrons through the tunnel oxide 105 layer where they are thereafter trapped in the silicon nanocrystal 104 floating gate. The trapped electrons act as an additional source of electrical potential between the gate 101 and the current channel in the silicon substrate 108, the extent of the source of the potential (i.e., the amount of stored charge) to determine the logical state of the silicon nanocrystal memory device 100.
FIG. 1 illustrates a substrate cross section of a silicon nanocrystal memory device 100 including a gate 101, drain 102, source 103, silicon nanocrystals 104, tunnel oxide 105, current channel 106 in the silicon substrate 108 and control oxide 107. The silicon nanocrystal 104 floating gate (scale increased for illustration only) is located between the control oxide 107 and the tunnel oxide 105, and relies on hot electron injection and Fowler-Nordheim electron tunneling through the thin tunnel oxide 105 to accumulate and disperse charge. An electrical potential, usually between 10 and 13 volts, can be applied to the gate 101 to excite electrons through the tunnel oxide 105 layer where they are thereafter trapped in the silicon nanocrystal 104 floating gate. The trapped electrons act as an additional source of electrical potential between the gate 101 and the current channel in the silicon substrate 108, the extent of the source of the potential (i.e., the amount of stored charge) to determine the logical state of the silicon nanocrystal memory device 100.
FIG. 1 also illustrates one-dimensional band diagrams for write 110, store 111, and erase 112 functions of the silicon nanocrystal memory device 100. The silicon nanocrystals 104, however, exhibit many interface states, and are subsequently unstable and highly sensitive to back end processing steps. In other words, despite theoretical promise, the silicon nanocrystal memory device is difficult in production with high parametric yield.
FIG. 2 is a schematic illustration of a substrate 200 cross section of a carbon nanotube nanocrystal memory of an embodiment.. In an embodiment, substrate 200 is n+ silicon. Formed on the substrate 200 is a dielectric 201, in an embodiment silicon dioxide. A carbon nanotube 202 is formed on the dielectric 201 and operates as a channel region. Metal electrodes 205 provide electrical contacts to the carbon nanotube 202 at two separate locations. Nanocrystals 204 are formed adjacent to the carbon nanotube 202 and between electrodes 205. The nanocrystals 204 operate as a floating gate as they are separated from the carbon nanotube 202 by a tunnel oxide 203. The structure further includes a gate 207 separated from the nanocrystals 204 by a control oxide 206.
FIG. 2 is a schematic illustration of a substrate 200 cross section of a carbon nanotube nanocrystal memory of an embodiment.. In an embodiment, substrate 200 is n+ silicon. Formed on the substrate 200 is a dielectric 201, in an embodiment silicon dioxide. A carbon nanotube 202 is formed on the dielectric 201 and operates as a channel region. Metal electrodes 205 provide electrical contacts to the carbon nanotube 202 at two separate locations. Nanocrystals 204 are formed adjacent to the carbon nanotube 202 and between electrodes 205. The nanocrystals 204 operate as a floating gate as they are separated from the carbon nanotube 202 by a tunnel oxide 203. The structure further includes a gate 207 separated from the nanocrystals 204 by a control oxide 206.
The nanocrystals 204 operating as a floating gate can be compared to a valve that controls the flow of charge carriers through the carbon In operation, the carbon nanotube 202 is a one-dimensional conductor spanning the electrodes 205. The conductivity of the carbon nanotube 202 depends in part on the charge stored by the nanocrystals 204 functioning as an array of discrete floating gates adjacent to the carbon nanotube 202.
Said alternatively, based on the amount of current that the nanocrystal 204 floating gate allows through the carbon nanotube 202, external circuit elements (not illustrated) can determine if the nanotube nanocrystal floating gate memory of an embodiment is storing a logical "1" or a logical "0." Further, as the carbon nanotube 202 is one-dimensional, the preferred percolation current of a two-dimensional nanocrystal array on a two dimensional current channel in the silicon substrate as introduced above is substantially eliminated.
