Tokyo Electron Limited (Tokyo, JP) earned U.S. Patent 7,642,201 for an Ionized Physical Vapor Deposition (IPVD) system that is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.
According to Tokyo Electron inventors Frank M. Cerio Jr., Shigeru Mizuno, Tsukasa Matsuda and Adam Selsey, the deposition process is such that the overhang or overburden is eliminated or minimized, reducing the reliance on or need for the etch step as an overhang control. In various embodiments, the process involves depositing a thin layer of a barrier metal such as tantalum (Ta) or tantalum-nitride (TaN). For example, the barrier deposition process can be followed by a seed layer process and/or a dry-filling process in which a metal such as copper is used.
In the metallization of high aspect ratio vias and trenches on semiconductor substrates, it is required that the barrier and seed layer have good sidewall coverage.
Ionized Physical Vapor Deposition (IPVD) is used for barrier and seed layer metallization in advanced IC substrates. Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, as the geometries shrink and as the via dimensions go down below 0.15 micrometers, ionized deposition requirements become more critical. Therefore, it is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized.
Ionized Physical Vapor Deposition (IPVD) is used for barrier and seed layer metallization in advanced IC substrates. Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, as the geometries shrink and as the via dimensions go down below 0.15 micrometers, ionized deposition requirements become more critical. Therefore, it is highly desirable to have an ionized PVD process where bottom and sidewall coverage are well balanced and overhang is minimized.
However there is a need to further control step coverage of the metal or the overhang that typically develops during the deposition step. Tokyo Electrons nanofabrication apparatus provides a method of operating a deposition system to perform sequential tantalum-nitride deposition sequence comprising one or more Low Net Deposition (LND) processes and one or more No Net Deposition (NND) processes.
Tokyo Electron developed a method of operating an ionized physical vapor deposition (iPVD) system to deposit barrier layer material into nanometer features on a patterned substrate on a substrate holder within a processing chamber in the iPVD system. In some embodiments, a four-step procedure can be performed at lower temperatures, and the procedure can include one or more Low Net Deposition (LND) iPVD processes and one or more No Net Deposition (NND) iPVD process.
For example, the LND process can be characterized by a deposition rate between approximately +5 nanometers per minute and approximately +15 nanometers per minute in the field area of the substrate, and the NND process can be characterized by a deposition rate between approximately -5 nanometers per minute and approximately +5 nanometers per minute in the field area of the substrate. During the four-step procedure, process parameters are adjusted to establish an ultra-low deposition rate in a field area of the patterned substrate. The method may also be used, for example, to repair a barrier.
The field area refers to the upper surface of the substrate being processed and is the surface into which the high aspect ratio vias and trenches extend. An ultra-low deposition rate is a deposition rate of less than about 15 nanometers per minute in the field area.
An iPVD processing system can be used for the barrier deposition processes. These processes can be typically performed in the vacuum processing chamber of an iPVD apparatus in which the substrate to be coated is held on a support. A high-density plasma is maintained in the chamber in a processing gas, which can be, for example, an inert gas into which metal or other coating material vapor has been introduced, usually by sputtering. The high-density plasma is usually ionized by coupling RF energy into the process gas, often by an inductive coupling from outside of the chamber.
For example, the LND process can be characterized by a deposition rate between approximately +5 nanometers per minute and approximately +15 nanometers per minute in the field area of the substrate, and the NND process can be characterized by a deposition rate between approximately -5 nanometers per minute and approximately +5 nanometers per minute in the field area of the substrate. During the four-step procedure, process parameters are adjusted to establish an ultra-low deposition rate in a field area of the patterned substrate. The method may also be used, for example, to repair a barrier.
The field area refers to the upper surface of the substrate being processed and is the surface into which the high aspect ratio vias and trenches extend. An ultra-low deposition rate is a deposition rate of less than about 15 nanometers per minute in the field area.
An iPVD processing system can be used for the barrier deposition processes. These processes can be typically performed in the vacuum processing chamber of an iPVD apparatus in which the substrate to be coated is held on a support. A high-density plasma is maintained in the chamber in a processing gas, which can be, for example, an inert gas into which metal or other coating material vapor has been introduced, usually by sputtering. The high-density plasma is usually ionized by coupling RF energy into the process gas, often by an inductive coupling from outside of the chamber.
The RF energy ionizes both the process gas and a fraction of the coating material, which may be to a low plasma potential of only a few volts, but may be higher. The processing gas and the ionized coating material can then be directed onto the substrate by control of the bias on the substrate, to coat and not etch the substrate.
For the LND processes of the present invention, an iPVD process is run, but with the deposition rates reduced as explained in the examples below. The parameters of the iPVD process are controlled to produce the LND result on the plasma-facing surface of the substrate, or field area of the substrate. When so controlled, the iPVD process produces the desired result of deposition of a barrier layer or a seed layer, without producing overhangs around the feature openings.
Tokyo Electron’s deposition technique involves the use of an iPVD system to metallize high aspect ratio vias and trenches by depositing ionized metal with a flux to the field area surface of the substrate that produces a flux to the sidewall of the feature. This technique does not rely on an etch sequence to control the conformality of the metal.
Tokyo Electron’s deposition technique involves the use of an iPVD system to metallize high aspect ratio vias and trenches by depositing ionized metal with a flux to the field area surface of the substrate that produces a flux to the sidewall of the feature. This technique does not rely on an etch sequence to control the conformality of the metal.
Tokyo Electron’s invention is distinctly different from prior art which teaches high DC powers with high RF bias powers for increased conformality or the case where several deposition and etch steps are performed within or in different vacuum chambers. This barrier deposition process is characterized by very low deposition rates. For example, the DC power can be reduced to reduce the deposition rate to less than 10 nm per minute.
Additionally, a range of RF substrate biases can be applied to the substrate during the barrier deposition process.
FIG. 3 illustrates a simplified flow diagram of a method of operating a deposition system to perform a barrier deposition process in accordance with an embodiment of Tokyo Electron's Process
FIG. 4 illustrates exemplary process results
FIG. 3 illustrates a simplified flow diagram of a method of operating a deposition system to perform a barrier deposition process in accordance with an embodiment of Tokyo Electron's Process
