University of Illinois Professor John A Rogers (Champaign, IL) and Professor Huang Yonggang along with fellow inventors Heung Cho Ko, Mark Stoykovich,Won Mook Choi, Jizhou Song, Jong Hyun Ahn and Dae Hyeong Kim created a wide range of stretchable, foldable and optionally printable, processes for making devices such as semiconductors, electronic circuits and other electronic components. The components are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. The processes and devices are detailed and lavishly illustrated in U.S. Patent Application 20100002402.
U.S. Patent Application 20100002402, FIG. 1. (A) Overview of the fabrication process for ultrathin CMOS circuits that exploit silicon nanoribbons, and enable extreme levels of bendability (third frame from the top) or fully reversible stretchability/compressibility (bottom frame on the right). (B-D) Optical images circuits on the carrier wafer and doped nanoribbons (inset) (B), on a thin rod after removal from this carrier (C) and in a wavy configuration on PDMS (D). (click on images to enlarge)
FIG. 38 illustrates a process for making a foldable and pop-up stretchable electronic device by (A) thermal transfer; and (B) mechanical deformation. Photographs of the devices are provided in C-E.
FIG. 3. (B) Circuit diagram of a differential amplifier (top left); output characteristics for various strain values (bottom left); optical images of a wavy differential amplifier in its as-fabricated state (top right) and under applied strain in a direction along the red arrow (bottom right).
FIG. 4. (A) Image of a `foldable` ultrathin Si-CMOS circuit that uses an encapsulating layer of PI, wrapped around the edge of a microscope cover slip. The inset shows a coarse cross sectional schematic view. (B) Images of twisted (top) and bent (bottom inset) wavy Si-CMOS circuit that uses a dual neutral plane design. The inset at the top shows a coarse cross sectional view. Optical micrographs of inverters at the center (bottom left) and edge (bottom right) of the sample in the twisted configuration shown in the top frame.
FIG. 5. Schematic diagram for circuit preparation procedures for foldable, stretchable, and printable electronic devices developed by University of Illinois Scientists
FIG. 17. Photographs of a hemispherical electronic eye camera and representative output image. A, Photograph of a hemispherical focal plane array (center) mounted on a printed circuit board (green), with external connection to a computer (not shown) through a ribbon cable (upper left). B, Photograph of the camera after integration with a transparent (for ease of viewing) hemispherical cap with a simple, single component imaging lens (top). C, Close-up photograph of the system in B, as viewed directly through the imaging lens.
FIG. 18. Process flow for efficient removal of the focal plane array from the SOI wafer. The key steps are d-h, in which a spin cast layer of polymer (polyimide for the results presented here) penetrates through predefined etch holes to keep most of the array suspended from the underlying silicon handle wafer after HF undercut etching of the buried oxide. This strategy avoids stiction that would otherwise frustrate the ability to lift off the array. The posts formed by the polymer prevent unwanted slipping or wrinkling of the array during the HF etching.
FIG. 41 Schematic comparison and overview of the fabrication process for wavy interconnected CMOS inverters using doped silicon nano-materials; (a) Sheet-type wavy inverters (b) Ultrathin CMOS islands connected with wavy PI bridges. (c) Ultrathin nMOS and pMOS devices connected with wavy PI and metal interconnects
