Harvard researchers have unveiled graphene P-N junctions for ultra-small devices. The potential market for this technology is the entire semiconductor chip industry. Silicon has transformed the digital world, but researchers continue to search for materials to make integrated circuits smaller, faster and cheaper.
High on the list of new materials is graphene – a 2D sheet of carbon just one atom thick. Bearing excellent material properties, such as fast electron conductivity, graphene is suited for creating components for flexible displays and ultrafast electronic transistors. Its planar geometry allows the fabrication of electronic devices and the tailoring of a variety of electrical properties. Because it is only one-atom thick, it can potentially be used to make ultra-small devices and further miniaturize electronics. The biggest challenge in exploiting graphene’s flexibility in computing applications is getting it to perform as a true semiconductor. While it can be considered a semiconductor like silicon, graphene lacks one crucial property – the ability to act as a switch. Without this, a chip will draw electricity continuously, unable to turnoff.
Harvard researchers Hugh Olen Hill Churchill, Charles M. Marcus and James Ryan Williams, have developed a locally-gated p-n junction in graphene. The charge density in the device is controlled by applying voltages to electrodes that are attached to the surface of the material. The positive electrode attracts electrons to the region of graphene below it, creating an area of excess negative charge (an n-type semiconductor). Similarly, the negative electrode repels electrons and creates an area of excess positive charge (a p-type semiconductor). The graphene now has p-type and n-type regions with a well defined “p-n junction” in the area between the two electrodes.
Using atomic layer deposition (ALD) to create an insulating layer, the Harvard team has solved the challenge of placing a tiny metal electrode (or local gate) very near to the surface of graphene without damaging the graphene or changing its electrical properties. Marcus and his team solve this problem by using atomic layer deposition (ALD) The graphene sheet itself rests on a silicon substrate coated with an insulating layer. The silicon acts as the second electrode controlling the p-n junction.
A major advantage of this technique is the creation of an insulating layer with a relatively high dielectric constant compared to other techniques using silicon oxide and PMMA. A high dielectric constant is important in very small electronic devices because it allows large electric fields to be applied without electrical breakdown occurring across the insulator. This novel fabrication technique opens the door to practical graphene transistors that could be much smaller and more efficient that today’s silicon-based devices. In addition, because graphene-based devices are very insensitive to temperature variations, device operation at a variety of temperatures (from 4K to room temperature) can be achieved with a wide array of p-n configurations.
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Reference Harvard Case #3180
