DSM Solutions, Inc. (Los Gatos, CA) reveals scalable device structures and processes for forming normally off junction field effect transistors (JFET) with 45 nanometer (nm) linewidths or less in U.S Patent 7,642,566.
At one micron line widths, power consumption for a one square centimeter integrated circuit was 5 watts. As line widths shrink to 45 nanometers, power consumption for the same size chip could rise to 1000 watts. This can destroy an integrated circuit which is not cooled properly and is clearly unacceptable for portable devices such as laptops, cell phones etc. This power consumption complicates the design process immensely because it requires additional circuitry to put idle transistors to sleep so they do not leak. This power consumption is only one of the problems caused by shrinking linewidths.
A problem with the JFET is that it is a normally on device. As such, it cannot be used to replace conventional CMOS transistors in today's integrated circuitry with the power leakage problems brought on by shrinking line widths. In order to substitute JFET's for CMOS to solve the power consumption problem at line widths of 45 nm and smaller, it is necessary to have a normally off JFET.
DSM Solutions has met the need for a new process to fabricate normally off JFETs and a device structure, both of which eliminate an etching problem and which will scale to smaller linewidths.
DSM Solutions has met the need for a new process to fabricate normally off JFETs and a device structure, both of which eliminate an etching problem and which will scale to smaller linewidths.
According to inventors DSM Madhukar B Vora and Ashok Kumar Kapoor, the contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
The process eliminates the etch step whose control is so imprecise as to cause probable damage to the gate region. The novelty of the technique is to deposit a layer of oxide on the top of the substrate after forming the active islands with the field oxide and implanting the P-well (or N-well in the case of a P-channel JFET).
Typically the oxide layer is 500 angstroms thick CVD oxide, but it could also be a "low-K" (low dielectric constant) oxide. Then the oxide layer is masked and etched to form holes where the poly source, drain, gate and substrate contacts are to be formed. The advantage of using low-K oxide over CVD oxide is that the etching of the low-K oxide for the source and drain holes will stop at the thermal oxide of the field oxide regions and not create a notch.
This notch will happen if etch overshoot of CVD oxide happens; such a notch is undesirable. The reason this notch is undesirable is because if etch overshoot occurs, the field oxide outside the active area defined by the field oxide is etched down below the surface of the substrate. This causes the gate poly to dip down and form sidewall PN contacts with the gate region which, if deep enough, can short to the gate-substrate junction. Then a layer of nitride is formed on top of the oxide to act as a polish stopper.
Nitride is very hard and it stops any polishing process at the nitride layer. After the holes are etched, a layer of polysilicon is deposited so as to fill the holes. The poly is then polished off until the polishing process stops at the nitride layer. Since the oxide layer is only approximately 500 angstroms (50 nm) thick typically (any reasonable depth for this layer can be picked as oxide is well behaved), the poly contacts are only 500 angstroms thick after the polishing process (or as thick as the oxide layer).
