In U.S. Patent Application 20100012925, Nantero Inc (Woburn, MA) inventors Claude L Bertin, Mitchell Meinhold, Steven L Konsek, Thomas Rueckes, and Frank Guo describe the process for fabricating hybrid carbon nanotube FET(CNFET)-FET Static RAM (SRAM).
The static ram memory cell includes two semiconductor-type field effect transistors (FETs), and two nanotube FETs (NTFETs). Each FET has a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions. The channel region is made of a second type of semiconductor material; each FET further has a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate.
The static ram memory cell includes two semiconductor-type field effect transistors (FETs), and two nanotube FETs (NTFETs). Each FET has a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions. The channel region is made of a second type of semiconductor material; each FET further has a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate.
The two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other. Each NTFET has a channel region made of at least one semiconductive nanotube, connected to a respective source and drain region of a corresponding NTFET. A first NTFET is connected to the drain or source of the first semiconductor-type FET and the second NTFET is connected to the drain or source of the second semiconductor-type FET.
