The Iranian researchers at University of Tehran in cooperation with colleagues from Khajeh Nasireddin-e-Toosi University of Technology (KNTU) managed to introduce an appropriate solution to speed up electronic nanoscale systems and reduce their power consumption.
The trend of dimension shrinking in silicon microelectronic industry has been following Moore's Law during recent decades, but physics fundamental problems in small dimensions caused changes to transistor linear dimension reductions.
"We conducted a research to analyze and present possible solutions within shifts towards instruments dimension shrinking and directed our attentions to the problems concerning design and optimization of such instruments," Farzan Jazayeri, one of the associated researchers said to the news service of INIC.
The main focus was on checking power consumption, speed, and stability of used circuits, he added.
"In this project, we used two Field Effect transistor gates instead of single gates. We managed to reduce power consumption and chip surface area (two important parameters in designing integrated circuits) simultaneously with power loss by applying new circuit methods in automatic gain control systems. Field effect diode instrument and link capacitor modeling was the first step in this research project," Jazayeri asserted.
In the second step, they used the mentioned instrument as VGA and also active load in an automatic gain control system.
According to Jazayeri, the reduction of short channel effects which mostly appear at small dimensions, DIBL phenomenon reduction, GIDL and Punch Through reduction, impurity atoms random oscillations reduction, power consumption reduction, chip surface area reduction, gain variation range extension in automatic gain control systems, and a hike in the system's speed by increasing frequency response are the results of this study.
You may find more details at IEICE Electronics Express, volume 6, pages 51 to 57, 2009
