Camtek Ltd. (Migdal Haemek, Israel) announced the introduction of a new semiconductor inspection tool focused on the special requirements of the LED Market.
Camtek's Condor 5LED is a new AOI (Automated Optical Inspection) system designed to provide solutions to a variety of requirements that are unique to LED semiconductor manufacturers.
The LED Market's special inspection requirements are characterized by 3-6 inch wafers, each of which may contain between 100 to over 200 thousand LED devices per wafer. Typically the wafer is made of a translucent compound semiconductor such as Gallium Arsenide, Gallium Phosphate and/or Indium Phosphate. The customers' defect specifications and unique inspection process raise a significant challenge for AOI suppliers to solve.
Camtek has already been addressing the special needs of this market for over two years and has designed solutions on a per customer basis, built into existing platforms. Camtek has installed 6 such systems in three countries in this time. The new Condor 5LED incorporates all Camtek's experience in this space, into a singular and focused designated solution, targeted at the LED Market.
Mr. Roy Porat, Camtek's General Manager commented: "The Condor 5LED will further entrench our leading position in this market segment. Throughout the past year, we have been benchmarked a number of times against competitors, and we have been chosen as the 'tool of choice' several times. The Condor 5LED will strengthen our position in this market, and will allow us to maintain and build on our technological leadership."
Mr. Porat concluded: "We are optimistic with regard to this segment in 2010. Given indications for significant growth from our customers in the LED Market, we aim to grow our business with the Condor 5LED in the coming quarters and years."
Camtek Ltd (NASDAQ and TASE: CAMT) provides automated solutions dedicated for enhancing production processes and yield, enabling our customers new technologies in three industries; Semiconductors, Printed Circuit Board (PCB) and IC Substrates.
Camtek addresses the specific needs of these industries with dedicated solutions based on a wide and advanced platform of technologies including intelligent imaging, image processing, ion milling and digital material deposition. Camtek's solutions range from micro-to-nano by applying its technologies to the industry-specific requirements.
The rush to secure intellectual property related to nanotechnology continues unabated. In the first week of January an estimated 102 nanotechnology patents were granted. At least 113 more nanotechnology related U.S. Patents were awarded on January 12, 2009.
Thirty of the newly awarded patents and their relation to nanotechnology are noted below. The patent number, assignees and patent titles arecited followed by brief descriptions of where or how nanotechnology is used.
Brother Kogyo Kabushiki Kaisha (Nagoya-shi, Aichi-ken, JP) Method of producing a piezoelectric actuator Piezoelectric actuator in which diffusion-preventive layer is formed of metal nano-particles having a particle size of not more than 50 nm.
Massachusetts Institute of Technology (Cambridge, MS) inventors William J.Arora, Fernando Castano, Anthony J Nichol and George BarbastathisThin membrane alignment method using patterned nanomagnets Nanofabrication process for lithographically patterned magnetic material. It is a way to build 3D nanostructures is by "stacking" 2D membranes or "folding" a large membrane into a layered structure. Nanomagnets may be made of iron, cobalt, nickel or any alloy consisting primarily of one or more of these metals.
Nanosys, Inc. (Palo Alto, CA) Nanocrystal doped matrixes A nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.
Instituto Mexicano del Petroleo (Mexico City, MX) Nanostructured titanium oxide material and its synthesis procedure New crystalline structure is the basic unit of construction of nanomaterials which are nanofibers, nanowires, nanorods, nanoscrolls and/or nanotubes. These nanomaterials are obtained from a precursor that is isostructural to the new crystalline structure. The precursor is composed of hydrogen titanate and/or a mixed sodium and hydrogen titanate. These titanates are the hydrogenated, protonated, hydrated and/or the alkalinized phases of the new crystalline structure. In addition, this invention also relates to the procedure of synthesis of the nanomaterials.Nanomaterials are used in catalysis and materials fields
Eastman Kodak Company (Rochester, NY) Multi-layer conductor with carbon nanotubes An electronically conductive article comprising at least one conductive carbon nanotube layer in contact with at least one conductive layer comprising electronically conductive polymer.
Rovcal, Inc. (Madison, WI) Separators for alkaline electrochemical cells Chemically synthesized agglomerates of a nano-CuO may also be used for the cathode. Such materials can be obtained from NanoScale Materials, Inc.
University of Florida Research Foundation, Inc. (Gainesville, FL) and Banyan Biomarkers (Alachua, FL) Biomarkers of liver injury Digests are analyzed using nanospray liquid chromatography online with tandem mass spectrometry (nano-LC/MSMS)
Sharp Laboratories of America, Inc. (Camas, WA) inventors Sheng TengHsu and Fengyan Zhang Nanotip capacitor A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips.
Elan Pharmaceuticals, Inc. (South San Francisco, CA) Acetyl 2-hydroxy-1, 3-diaminoalkanes The nano crystalline formulations typically afford greater bioavailability of drug compounds.
Pfizer Inc. (New York, NY) Substituted arylpyrazoles Compounds for pharmaceutical use may be administered as crystalline or amorphous products, for example, spray-dried dispersions or as produced by melt-extrusion or nano-milling. Compounds may be administered include oral administration by capsule, bolus, tablet, powders, lozenges, chews, multi and nanoparticulates, gels, solid solution
Kawamura Institute of Chemical Research (Sakura-shi, JP) Monodisperse silica spheres containing polyamine and process for producing the same Since polyethyleneimine is a strong ligand, metal ions can be concentrated within silica. Also, since polyethyleneimine can reduce noble metal ions to metal atoms, nanoparticles of noble metals can be conveniently immobilized within the silica. Since polyethyleneimine also has properties such as a sterilizing function, resistant to viruses, and the like, the spheres can also exhibit such properties. Therefore, the monodisperse silica spheres can be applied to various areas such as carriers for metal ions and/or nanometals, catalysts, antibacterial agent, disinfectants, antiviral agents, cosmetic products, and the like.
Nanosolar, Inc. (San Jose, CA) Nanostructured layer and fabrication methods Nanostructured layers with 10 nm to 50 nm pores spaced 10-50 nm apart, a method for making such nanostructured layers, optoelectronic devices having such nanostructured layers
David MichaelFeyler (Westwood, MA) Fake ID finder A device to magnify a driver's license sufficiently to view the micro printing, nano printing and Ultra Violet features for fine detailed inspection.
Chien-MinSung (Tansui, Taipei County 251, TW) Diamond LED devices and associated methods A way of forming epitaxially a substantially nanometer single crystal diamond layer on the SiC layer
Charles EricHunter; (Hilton Head Island, SC), Bernard L Ballou, Jr.;. (Raleigh, NC), Kelly C.Sparks; (Morrisville, NC), John H.Hebrank; (Durham, NC) Video distribution system Nanometer lasers are cost-effective for writing conventional CDs.
National Quality Care, Inc. (Los Angeles, CA) Wearable ultrafiltration device may use nanotechnology pump, microtechnology/micromachined pump, syringe pump
Regents of the University of California (Oakland, CA) Osmium diboride compounds and their uses Nanoindentation2. The osmium diboride compounds may be used in the same manner as other super hard material as a protective surface coating, a cutting or abrading tool surface coating or as an abrasive. measurements were thus performed on OsB
Hon Hai Precision Industry Co., Ltd. (Tu-Cheng, Taipei Hsien, TW) Protective film structure contains nano particles comprised of a material selected from the group consisting of carbon nano tubes, carbon nano sticks, carbon 60, carbon particles, nano-sized conductive metals, nano-sized semiconductors, and any combination thereof.
Vive Nano, Inc. (Toronto, CA) Producing nanoparticles using nanoscale polymer templates Methods of producing a composite nanoparticle comprising a nanoparticle confined within or associated with a shape-static polymeric material, which is itself a nanoparticle
A fluorescence quenching microscopy (FQM) image of graphene oxide (G-O) sheets on a glass substrate with a 30 nm thick fluorescein/PVP coating taken by a cheap consumer digital camera (Panasonic, DMC-FZ1). This image is representative of what can be seen by naked eye with FQM. Scale bar = 50 μm. The green background is from fluorescein emission.
Graphene based sheets have stimulated great interest due to their superior mechanical, electrical, and thermal properties. A general visualization method that allows quick observation of these single atomic layers would be highly desirable as it can greatly facilitate sample evaluation and manipulation, and provide immediate feedback to improve synthesis and processing strategies.
A Northwestern University team lead by assistant professor of materials science and engineering at the McCormick School of Engineering and Applied Science Jiaxing Huang and including Jaemyung Kim, Laura J. Cote, and Franklin Kim report that graphene based sheets can be made highly visible at a low cost under a fluorescence microscope by quenching the emission from a fluorescein dye coating, which can be conveniently removed afterward by rinsing without disrupting the sheets. They report their findings in Visualizing Graphene Based Sheets by Fluorescence Quenching Microscopy
They developed a general method for visualizing graphene based sheets on arbitrary substrates by fluorescence quenching microscopy (FQM). The fluorescence quenching mechanism eliminates the need for special substrates and even allows the direct observation of graphene based sheets in solution. It offers unprecedented imaging flexibility for characterizing graphene based materials.
Current imaging techniques for graphene based sheets are time consuming and rely on the use of special substrates and costly instruments. In contrast, the fluorescence quenching mechanism is no longer limited by the type of substrate. Graphene, reduced graphene oxide, or even graphene oxide sheets deposited on arbitrary substrates can now be readily visualized with good contrast for layer counting.
Direct observation of suspended sheets in solution was also demonstrated. The fluorescence quenching microscopy offers unprecedented imaging flexibility and could become a general tool for characterizing graphene based materials.
Images of mechanically exfoliated graphene on a SiO2/Si substrate taken by (a) AFM, (b) optical microscopy, and (c) FQM using PVP/fluorescein. All scale bars ) 10 μm.
Utilizing the strong fluorescence quenching effect, graphene based, single atomic layer carbon sheets can be visualized with a common fluorescence microscope by applying a dye dope polymer coating. The dye layer can be easily removed by washing after imaging without disrupting the underlying sheets.
FQM works with a wide range of fluorescent materials and polymers including resist materials used in photolithography and e-beam lithography. This makes FQM compatible with microfabrication processes. Therefore, FQM could greatly broaden the scope of single layer device fabrication since it can image these 2D sheets on arbitrary substrates. FQM enables high throughput, high contrast evaluation of graphene based
Their results were recently published in the Journal of the American Chemical Society.
In U.S. Patent Application 20090317336, Battelle Memorial Institute (Columbus, Ohio) inventors Amit Gupta (Richland WA), William C. Forsythe and Mark L Clark disclose a method and apparatus for generating high purity nanoparticles, including fullerenes, carbon nanotubes, titanium dioxide and cerium oxide (CeO) at high concentration
The apparatus uses a solid aerosol disperser in communication with a furnace tube having a vaporization chamber and a dilution chamber. A heating element surrounds the furnace tube. Heat from the heating element heats bulk materials contained within a gas flow in the vaporization chamber to a temperature sufficient to convert the bulk materials to a vapor phase.
Vaporized bulk materials are then moved to a dilution chamber, where an inert gas is introduced through a dilution gas port. The flow of the inert gas into the dilution chamber through the dilution gas port is sufficient to eject the bulk material from the exit of the dilution chamber, thereby condensing the bulk material into nano sized particles in a gas flow of sufficient volume to prevent agglomeration of the nano sized particles.
The nanomaterials generated by the apparatus are suitable for use in applications requiring high concentration and high purity, including inhalation toxicology studies, manufacturing applications, occupational safety and health studies, and as drug delivery systems.
The manufacturing method is particularly well suited and enables the generation of high concentrations of nano-sized particles of C60 aerosols. It is also well suited to the production of cerium oxide, carbon nanotubes, titanium dioxide, C70, C76, and C84. The apparatus features the use of a solid aerosol disperser.
While these commercially available solid aerosol dispersers can be configured to provide a flow of solid particles in a gaseous flow, the particle size of their output is not sufficiently small to meet the objectives of the Battelle apparatus.
For example, and not meant to be limiting, beginning by milling commercially available bulk material consisting of C60 particles supplied by SES Research, Houston, Tex., the solid aerosol disperser available from Battelle Memorial Institute (Columbus, Ohio), can then provide a constant flow of C60 having particles sized between about 1 .mu.m and about 1.5 .mu.m mass median aerodynamic diameter (MMAD) in a flow of nitrogen of about 6-6.5 LPM.
Battelle’s invention provides a method whereby those particles are reduced further in size while maintaining purity, such that the resulting particles are of less than 100 nm count median diameter (CMD) and do not exhibit chemical decomposition of C60 to an amorphous phase or to carbon black. Accordingly, the "nano sized particles" produced by the Battelle invention are defined herein as particles having less than 100 nm count median diameter (CMD).
Atomic Energy Council - Institute of Nuclear Energy Research (INER) (Taouyuan, TW) researchers Tsun-Neng Yang and Shan-Minga Lan discovered an environmentally friendly and economical method for manufacturing a red-light emitting diode (red-light LED) with a light emitting silicon (Si) base material that has Si quantum dots as luminescence centers, according to U.S. Patent 7,635,603
The manufacturing process produces red-light LEDs with economy, environmental protection and high efficiency. The LED luminescent strength is enhanced covering the whole red-light zone of a white-light spectrum. It can be produced at low cost, in a manner that is harmlessness to the environment and in a manner compatible with semiconductor manufacturing techniques. material.
The INER method for making a red-light LED with Si quantum dots involves a Si-rich non-stoichiometric silica film covering on a substrate that is grown through atmospheric pressure chemical vapor deposition (APCVP). Then, an annealing treatment to the substrate is processed to obtain a phase separation in the non-stoichiometric silica film so that a silica film having Si quantum dots as luminescence centers (Si QDs-SiO2 film) is formed on the substrate; and, then, the Si QDs-SiO2 film is put into a vacuum stove for a surface treatment under a temperature between 700 and 1000 Celsius degrees in an environment of oxygen gas added with graphite. Accordingly, a novel method for making a red-light LED having Si quantum dots is obtained.
In the early 1960s, a first red-light LED using a ternary alloy of GaAsP was successfully obtained. In 1980s, a LED using AlGaAs was successfully developed with enhanced light emitting efficiency. In 1990s, Hewlett-Packard Co. and Toshiba Co. further developed a LED with high efficiency using a quaternary alloy of AlGaInP. Yet, the manufactures of these ternary or even quaternary alloys are complex and the materials used include some rare or even poisonous heavy metals, such as Ga, As, P, etc.
The above prior arts use ternary or quaternary alloys to obtain red-light LEDs; but those ternary or quaternary alloys are rare or poisonous heavy metals at the same time. The prior arts do not provide low-cost, environmentally friendly means for manufacturing low cost red LEDs.
DARPA is soliciting innovative research proposals in the area of grating-based integrated circuit layout design and patterning. The goal of the Gratings of Regular Arrays and Trim Exposures (GRATE) program is to develop revolutionary new circuit design methodologies combined with grating-based lithography tools to enable cost effective low volume nanofabrication for Department of Defense (DoD) applications. $15 million is available in research grants in this three year-three phase program.
The table and figure below indicate the scope of the three phase GRATE project. (click to enlarge)
The novel circuit design methodologies will enable simplified physical layout implementation of circuits by leveraging extremely regular geometries. Overall circuit densities and performance will not be sacrificed when utilizing these new design approaches. These simplified circuit design geometries will be implemented using ultra-high-resolution grating patterns which can be fabricated at high throughput using either mask-based or maskless (interference) lithography.
Cost effective low volume microfabrication will be achieved by lowering the design and fabrication costs of custom application-specific integrated circuits (ASICs), enabling maskless interference-based patterning with practical throughputs, and improving fabrication yield resulting from regular circuit patterns. See the full DARPA-BAA-10-12 document: DARPA-BAA-10-12_GRATE_Final For Posting_18Dec09.pdf (198.12 Kb)
DARPA seeks innovative proposals in the following Areas of Interest:
Technical Area I. GRATE for Digital Designs:
The grating-based design and patterning technology will be developed and applied to digital logic and memory. The main goal of this thrust is to develop highly regular grating-based digital standard cells without a significant area or performance penalty. These design tasks will include development of CAD tools enabling regular geometry designs and software tools for converting legacy designs into regular geometry based layouts. In addition to these predominantly design based tasks, some fabrication process development to improve the pattern densities achievable with grating geometries is also envisioned. Demonstration vehicles will include typical digital “standard cells,” circuit blocks (SRAMS, latches, I/Os) and basic IC demos. It is hoped the GRATE paradigm will enable the scaling of current digital process technology by 2 nodes beyond current state of the art using existing lithography tools and masks. This corresponds to a density increase of 4X (area reduction to 25% of original area).
Technical Area II. GRATE for Analog/RF-Mixed Signal Designs:
The grating-based design and patterning technology will be developed and applied to analog/RF-mixed signal circuits. The main goal of this thrust is to enable the scaling of current RF technology patterning two nodes beyond current state-of-the- art using existing tools and masks. This will be accomplished by scaling the feature size of RF transistors (such as the emitter dimension in a bipolar transistor). The tasks here will involve grating-based design methodologies, fabrication “process extensions” to enable efficient grating-based patterning, and mask-based “trim” and “stitch” of the grating patterns into the desired RF circuit patterns. The demonstration vehicles will include high-speed RF (Bipolar/BiCMOS) devices (≥ 300GHz cutoff frequencies) and RF circuit blocks.
NOTE: Proposers may bid either a single technical area alone or both technical areas; however, if proposing to both areas, each shall be priced separately.
PROGRAM SCOPE
The main technical challenges of this program include methodologies to decompose complex circuit designs into regular grating patterns and customizing these gratings with the required area-efficient interconnects; the development of large area (wafer-scale), high resolution grating patterning technology; and the pairing of this capability with the appropriate form of mask-based or maskless trimming/stitching steps. Design methodologies must take maximum advantage of the benefits of extremely regular geometry patterns and allow efficient automated grating-based design and verification of state-of-the-art ICs. Software tools must also be developed for automated conversion of legacy designs to grating-based design layouts.
To address these challenges, the GRATE program is constructed as a multi-year program that will start with the development of grating-based design and patterning approaches, followed by implementation of these techniques to fabricate actual circuit patterns. Finally, the GRATE program will demonstrate these design and patterning techniques by fabricating functional digital logic/memory cells in the Digital Technical Area and Analog RF/Mixed-Signal circuits in the Analog Technical Area.
The Period of Performance is three years and the plan for the three-phase program is:
Phase I will focus on development of grating-based 1D designs primarily through simulation. The tasks will include 1D design of logic/memory “standard cells” and RF/Mixed Signal circuit modules; development of fabrication “process extensions” to enable dense local interconnect; and demonstration of “trim/stitch” processes used to customize gratings into circuit patterns. The overall goal is to enable the scaling of existing lithography tools and masks by 2 technology nodes.
Phase II will focus on demonstration of grating-based design and fabrication, emphasizing experimental verification of desired patterns. The demonstration vehicles will include digital logic/memory “standard cells” and high speed RF modules in state-of-the-art CMOS or BiCMOS technologies. Key tasks in this phase include developing the required grating and trim masks; demonstration of fabrication process extensions to enable dense local interconnect; grating-based design methodology; demonstration of grating-based and RF circuit patterns; and software development to help enable grating-based designs and convert layouts from standard (2D) to grating-based (1D) layout styles. Third party independent
Phase III will focus on demonstration of grating-based manufacturing potential by demonstrating digital logic/memory functional blocks and high speed analog RF/Mixed-Signal circuit modules. The novel grating-based design and fabrication capabilities will be made available to DoD designers. There are several ways in which this can occur. Grating-based design practice coupled with the enabling software tools could be offered.
A multi-project wafer run based on GRATE concepts might also be offered in this phase. In the case of a multi-project wafer offering, a Program “option” may be bid which includes funds beyond the scope of this particular solicitation. Independent third-party evaluation of both the digital and analog design approaches will continue in this phase. In addition to the fabrication demonstrations, grating-based Computer-Aided-Design (CAD) tools will be developed and become available to the DoD design community for work at leading edge technology nodes.
The major output of this program will include GRATE design methodologies and enabling design tools, layout conversion software (2D to 1D), process extensions, and enabling dense grating-based patterning. These output items will be regularly evaluated by government selected independent third-party designers (not related to the program performers) throughout the lifetime of the program. It is envisioned that grating-based design tools and possibly multi-project wafer (MPW) offerings will be made available to DoD designers at the end of this Program.
Full DARPA-BAA-10-12 document
Type: Other (Draft RFPs/RFIs, Responses to Questions, etc..)
