DARPA is soliciting innovative research proposals in the area of grating-based integrated circuit layout design and patterning. The goal of the Gratings of Regular Arrays and Trim Exposures (GRATE) program is to develop revolutionary new circuit design methodologies combined with grating-based lithography tools to enable cost effective low volume nanofabrication for Department of Defense (DoD) applications. $15 million is available in research grants in this three year-three phase program.
The table and figure below indicate the scope of the three phase GRATE project. (click to enlarge)
The novel circuit design methodologies will enable simplified physical layout implementation of circuits by leveraging extremely regular geometries. Overall circuit densities and performance will not be sacrificed when utilizing these new design approaches. These simplified circuit design geometries will be implemented using ultra-high-resolution grating patterns which can be fabricated at high throughput using either mask-based or maskless (interference) lithography.
Cost effective low volume microfabrication will be achieved by lowering the design and fabrication costs of custom application-specific integrated circuits (ASICs), enabling maskless interference-based patterning with practical throughputs, and improving fabrication yield resulting from regular circuit patterns. See the full DARPA-BAA-10-12 document: DARPA-BAA-10-12_GRATE_Final For Posting_18Dec09.pdf (198.12 Kb)
DARPA seeks innovative proposals in the following Areas of Interest:
Technical Area I. GRATE for Digital Designs:
The grating-based design and patterning technology will be developed and applied to digital logic and memory. The main goal of this thrust is to develop highly regular grating-based digital standard cells without a significant area or performance penalty. These design tasks will include development of CAD tools enabling regular geometry designs and software tools for converting legacy designs into regular geometry based layouts. In addition to these predominantly design based tasks, some fabrication process development to improve the pattern densities achievable with grating geometries is also envisioned. Demonstration vehicles will include typical digital “standard cells,” circuit blocks (SRAMS, latches, I/Os) and basic IC demos. It is hoped the GRATE paradigm will enable the scaling of current digital process technology by 2 nodes beyond current state of the art using existing lithography tools and masks. This corresponds to a density increase of 4X (area reduction to 25% of original area).
Technical Area II. GRATE for Analog/RF-Mixed Signal Designs:
The grating-based design and patterning technology will be developed and applied to analog/RF-mixed signal circuits. The main goal of this thrust is to enable the scaling of current RF technology patterning two nodes beyond current state-of-the- art using existing tools and masks. This will be accomplished by scaling the feature size of RF transistors (such as the emitter dimension in a bipolar transistor). The tasks here will involve grating-based design methodologies, fabrication “process extensions” to enable efficient grating-based patterning, and mask-based “trim” and “stitch” of the grating patterns into the desired RF circuit patterns. The demonstration vehicles will include high-speed RF (Bipolar/BiCMOS) devices (≥ 300GHz cutoff frequencies) and RF circuit blocks.
NOTE: Proposers may bid either a single technical area alone or both technical areas; however, if proposing to both areas, each shall be priced separately.
PROGRAM SCOPE
The main technical challenges of this program include methodologies to decompose complex circuit designs into regular grating patterns and customizing these gratings with the required area-efficient interconnects; the development of large area (wafer-scale), high resolution grating patterning technology; and the pairing of this capability with the appropriate form of mask-based or maskless trimming/stitching steps. Design methodologies must take maximum advantage of the benefits of extremely regular geometry patterns and allow efficient automated grating-based design and verification of state-of-the-art ICs. Software tools must also be developed for automated conversion of legacy designs to grating-based design layouts.
To address these challenges, the GRATE program is constructed as a multi-year program that will start with the development of grating-based design and patterning approaches, followed by implementation of these techniques to fabricate actual circuit patterns. Finally, the GRATE program will demonstrate these design and patterning techniques by fabricating functional digital logic/memory cells in the Digital Technical Area and Analog RF/Mixed-Signal circuits in the Analog Technical Area.
To address these challenges, the GRATE program is constructed as a multi-year program that will start with the development of grating-based design and patterning approaches, followed by implementation of these techniques to fabricate actual circuit patterns. Finally, the GRATE program will demonstrate these design and patterning techniques by fabricating functional digital logic/memory cells in the Digital Technical Area and Analog RF/Mixed-Signal circuits in the Analog Technical Area.
The Period of Performance is three years and the plan for the three-phase program is:
Phase I will focus on development of grating-based 1D designs primarily through simulation. The tasks will include 1D design of logic/memory “standard cells” and RF/Mixed Signal circuit modules; development of fabrication “process extensions” to enable dense local interconnect; and demonstration of “trim/stitch” processes used to customize gratings into circuit patterns. The overall goal is to enable the scaling of existing lithography tools and masks by 2 technology nodes.
Phase II will focus on demonstration of grating-based design and fabrication, emphasizing experimental verification of desired patterns. The demonstration vehicles will include digital logic/memory “standard cells” and high speed RF modules in state-of-the-art CMOS or BiCMOS technologies. Key tasks in this phase include developing the required grating and trim masks; demonstration of fabrication process extensions to enable dense local interconnect; grating-based design methodology; demonstration of grating-based and RF circuit patterns; and software development to help enable grating-based designs and convert layouts from standard (2D) to grating-based (1D) layout styles. Third party independent
Phase III will focus on demonstration of grating-based manufacturing potential by demonstrating digital logic/memory functional blocks and high speed analog RF/Mixed-Signal circuit modules. The novel grating-based design and fabrication capabilities will be made available to DoD designers. There are several ways in which this can occur. Grating-based design practice coupled with the enabling software tools could be offered.
A multi-project wafer run based on GRATE concepts might also be offered in this phase. In the case of a multi-project wafer offering, a Program “option” may be bid which includes funds beyond the scope of this particular solicitation. Independent third-party evaluation of both the digital and analog design approaches will continue in this phase. In addition to the fabrication demonstrations, grating-based Computer-Aided-Design (CAD) tools will be developed and become available to the DoD design community for work at leading edge technology nodes.
A multi-project wafer run based on GRATE concepts might also be offered in this phase. In the case of a multi-project wafer offering, a Program “option” may be bid which includes funds beyond the scope of this particular solicitation. Independent third-party evaluation of both the digital and analog design approaches will continue in this phase. In addition to the fabrication demonstrations, grating-based Computer-Aided-Design (CAD) tools will be developed and become available to the DoD design community for work at leading edge technology nodes.
The major output of this program will include GRATE design methodologies and enabling design tools, layout conversion software (2D to 1D), process extensions, and enabling dense grating-based patterning. These output items will be regularly evaluated by government selected independent third-party designers (not related to the program performers) throughout the lifetime of the program. It is envisioned that grating-based design tools and possibly multi-project wafer (MPW) offerings will be made available to DoD designers at the end of this Program.
Full DARPA-BAA-10-12 document
Type: Other (Draft RFPs/RFIs, Responses to Questions, etc..)
Label: Full DARPA-BAA-10-12 document
Posted Date: December 18, 2009
Description: Full DARPA-BAA-10-12 document
Contracting Office Address:
3701 North Fairfax Drive
Arlington, Virginia 22203-1714
Arlington, Virginia 22203-1714
Primary Point of Contact.:
Michael C. Fritze,
Program Manager, MTO
