LOTS of Energy Program Goal Is Improved Portable Power for Military, DARPA Grants Available in 2010 for R&D

DARPA is soliciting innovative proposals to develop revolutionary new approaches to portable energy sources. The proposed energy sources must be explicitly capable of handling arbitrary power loads of average power between 5 and 50 watts which may also contain significant (up 100-watts) transient spikes.

 The Department of Defense (DoD) is critically dependent on portable electronics and, by extension, portable energy sources such as batteries. However, the actual energy output of state-of-the-art (SOA) battery technologies, such as the BA5590 LiSO₂ primary and BB2590 Li-ion secondary systems, fall short of their projected energy capacity under load, limiting run time of DoD electronic systems to as little as 20% of theoretical capability.  This operational inefficiency increases the number of batteries soldiers must carry in the field and also limits implementation of hybridization and distributed power concepts for DoD ground, aerial, and maritime vehicle platforms.

 The DARPA Limits Of Thermodynamic Storage (LOTS) of Energy program seeks to address inefficiencies in energy extraction by developing technologies that are capable of delivering the full expected run time out of a SOA portable energy source.  Utilizing the X590 form factor -- BA5590 for primary or BB2590 for secondary energy sources -- as a common initial goal, the LOTS of Energy program seeks to aggressively improve the performance of portable energy sources for the DoD.  For the purposes of this BAA, form factor is defined as the characteristic volume, weight voltage, environmental operating parameters, but NOT maximum current, maximum power, nor energy density.   

Competitive proposals to the LOTS of Energy program will present a development plan for portable energy sources which innately or discretely hybridize different technologies in order to maximize energy extraction efficiency while meeting load power profiles having significant transient fluctuations.  It is anticipated that this may require developing novel electrodes, new electrolytes, advanced separator membranes, and/or novel power management circuitry for technologies such as electrochemical double layer capacitors, asymmetric electrochemical capacitors, and/or novel multi-functional electrochemical cells. 

The proposed energy sources must match the X590 form factor without any additional cables or changes to the external equipment powered by the energy source.  Specifically, DARPA seeks to maximize the utilization of portable energy sources (batteries, etc.) up to their theoretical limit under real load power profiles which include significant transient discharging and/or charging power spikes.  All possible approaches, and combinations of approaches, will be considered including, but not limited to:

• hybridization via discrete components within the form factor of the energy source (e.g.: packaged electrochemical capacitor plus packaged battery)


• innate hybridization via development of multi-functional electrochemical cells (e.g.: a cell with both capacitive and faradaic energy storage functions)


•  performance optimization via use of power management circuits

Hybridizing new technologies with SOA energy sources such as commercially available or prototype batteries is a valid means to achieve the program goals.  While the X590 form factor is the initial goal, the proposed technology should be explicitly compatible with hybridization to a variety of energy sources (batteries, fuel cells, Stirling engines, etc.) via straightforward iterative engineering of packaging, connections, etc.

The energy storage technology must be capable of being produced in a commercial process which is economically scalable.  Specifically excluded is research that primarily results in evolutionary improvements to the existing SOA.  However, integration of low-cost disposable power management circuits to fully utilize the energy storage of other high-risk improvements is specifically encouraged as part of the overall proposed solution.

Collaborative efforts/teaming are encouraged. Collaborative efforts/teaming are encouraged. A teaming website, http://www.sainc.com/LOTSTeaming, will facilitate the formation of teams with the necessary expertise

DARPA-BAA-10-15
Type: Other (Draft RFPs/RFIs, Responses to Questions, etc..)
Posted Date: November 18, 2009

BAA DARPA-BAA-10-15.doc (354.00Kb)
DARPA-BAA-10-15 Appendix A and B
Type: Other (Draft RFPs/RFIs, Responses to Questions, etc..)
Posted Date: November 18, 2009

Appendix A and B.pdf (461.72 Kb)

Description: DARPA-BAA-10-15 Appendix A and B

Mod 1 DARPA-BAA-10-15.doc (41.00 Kb)
Description: Modification 1 - DARPA-BAA-10-1

Points of Contact

The Technical POC for this effort is Brian Holloway.

E-mail:  DARPA-BAA-10-15@darpa.mil

The BAA Administrator for this effort can be reached at:

Electronic mail:  DARPA-BAA-10-15@darpa.mil

DARPA/DSO

ATTN:  DARPA-BAA-10-15

3701 North Fairfax Drive

Arlington, VA  22203-1714

Email:  DARPA-BAA-10-15@darpa.mil

DARPA Offers $15 Million in GRATE Project Call for Proposals to Improve Nano Lithography Tools for Circuit Design

DARPA is soliciting innovative research proposals in the area of grating-based integrated circuit layout design and patterning. The goal of the Gratings of Regular Arrays and Trim Exposures (GRATE) program is to develop revolutionary new circuit design methodologies combined with grating-based lithography tools to enable cost effective low volume nanofabrication for Department of Defense (DoD) applications.  $15 million is available in research grants in this three year-three phase program.

The table and figure below indicate the scope of the three phase GRATE project. (click to enlarge)

The novel circuit design methodologies will enable simplified physical layout implementation of circuits by leveraging extremely regular geometries. Overall circuit densities and performance will not be sacrificed when utilizing these new design approaches. These simplified circuit design geometries will be implemented using ultra-high-resolution grating patterns which can be fabricated at high throughput using either mask-based or maskless (interference) lithography.

Cost effective low volume microfabrication will be achieved by lowering the design and fabrication costs of custom application-specific integrated circuits (ASICs), enabling maskless interference-based patterning with practical throughputs, and improving fabrication yield resulting from regular circuit patterns. See the full DARPA-BAA-10-12 document: DARPA-BAA-10-12_GRATE_Final For Posting_18Dec09.pdf (198.12 Kb)

DARPA seeks innovative proposals in the following Areas of Interest:

Technical Area I. GRATE for Digital Designs:

The grating-based design and patterning technology will be developed and applied to digital logic and memory. The main goal of this thrust is to develop highly regular grating-based digital standard cells without a significant area or performance penalty. These design tasks will include development of CAD tools enabling regular geometry designs and software tools for converting legacy designs into regular geometry based layouts. In addition to these predominantly design based tasks, some fabrication process development to improve the pattern densities achievable with grating geometries is also envisioned. Demonstration vehicles will include typical digital “standard cells,” circuit blocks (SRAMS, latches, I/Os) and basic IC demos. It is hoped the GRATE paradigm will enable the scaling of current digital process technology by 2 nodes beyond current state of the art using existing lithography tools and masks. This corresponds to a density increase of 4X (area reduction to 25% of original area).

Technical Area II. GRATE for Analog/RF-Mixed Signal Designs:

The grating-based design and patterning technology will be developed and applied to analog/RF-mixed signal circuits. The main goal of this thrust is to enable the scaling of current RF technology patterning two nodes beyond current state-of-the- art using existing tools and masks. This will be accomplished by scaling the feature size of RF transistors (such as the emitter dimension in a bipolar transistor). The tasks here will involve grating-based design methodologies, fabrication “process extensions” to enable efficient grating-based patterning, and mask-based “trim” and “stitch” of the grating patterns into the desired RF circuit patterns. The demonstration vehicles will include high-speed RF (Bipolar/BiCMOS) devices (≥ 300GHz cutoff frequencies) and RF circuit blocks.

NOTE: Proposers may bid either a single technical area alone or both technical areas; however, if proposing to both areas, each shall be priced separately.

PROGRAM SCOPE

The main technical challenges of this program include methodologies to decompose complex circuit designs into regular grating patterns and customizing these gratings with the required area-efficient interconnects; the development of large area (wafer-scale), high resolution grating patterning technology; and the pairing of this capability with the appropriate form of mask-based or maskless trimming/stitching steps. Design methodologies must take maximum advantage of the benefits of extremely regular geometry patterns and allow efficient automated grating-based design and verification of state-of-the-art ICs. Software tools must also be developed for automated conversion of legacy designs to grating-based design layouts.

To address these challenges, the GRATE program is constructed as a multi-year program that will start with the development of grating-based design and patterning approaches, followed by implementation of these techniques to fabricate actual circuit patterns. Finally, the GRATE program will demonstrate these design and patterning techniques by fabricating functional digital logic/memory cells in the Digital Technical Area and Analog RF/Mixed-Signal circuits in the Analog Technical Area.

The Period of Performance is three years and the plan for the three-phase program is:

                         

                        Phase I will focus on development of grating-based 1D designs primarily through simulation. The tasks will include 1D design of logic/memory “standard cells” and RF/Mixed Signal circuit modules; development of fabrication “process extensions” to enable dense local interconnect; and demonstration of “trim/stitch” processes used to customize gratings into circuit patterns. The overall goal is to enable the scaling of existing lithography tools and masks by 2 technology nodes.

                         

                        Phase II will focus on demonstration of grating-based design and fabrication, emphasizing experimental verification of desired patterns. The demonstration vehicles will include digital logic/memory “standard cells” and high speed RF modules in state-of-the-art CMOS or BiCMOS technologies. Key tasks in this phase include developing the required grating and trim masks; demonstration of fabrication process extensions to enable dense local interconnect; grating-based design methodology; demonstration of grating-based and RF circuit patterns; and software development to help enable grating-based designs and convert layouts from standard (2D) to grating-based (1D) layout styles. Third party independent

                        Phase III will focus on demonstration of grating-based manufacturing potential by demonstrating digital logic/memory functional blocks and high speed analog RF/Mixed-Signal circuit modules. The novel grating-based design and fabrication capabilities will be made available to DoD designers. There are several ways in which this can occur. Grating-based design practice coupled with the enabling software tools could be offered.

A multi-project wafer run based on GRATE concepts might also be offered in this phase. In the case of a multi-project wafer offering, a Program “option” may be bid which includes funds beyond the scope of this particular solicitation. Independent third-party evaluation of both the digital and analog design approaches will continue in this phase. In addition to the fabrication demonstrations, grating-based Computer-Aided-Design (CAD) tools will be developed and become available to the DoD design community for work at leading edge technology nodes.

The major output of this program will include GRATE design methodologies and enabling design tools, layout conversion software (2D to 1D), process extensions, and enabling dense grating-based patterning. These output items will be regularly evaluated by government selected independent third-party designers (not related to the program performers) throughout the lifetime of the program. It is envisioned that grating-based design tools and possibly multi-project wafer (MPW) offerings will be made available to DoD designers at the end of this Program.

Full DARPA-BAA-10-12 document

Type: Other (Draft RFPs/RFIs, Responses to Questions, etc..)

Label:  Full DARPA-BAA-10-12 document

Posted Date: December 18, 2009

DARPA-BAA-10-12_GRATE_Final For Posting_18Dec09.pdf (198.12 Kb)

Description: Full DARPA-BAA-10-12 document

Contracting Office Address:

3701 North Fairfax Drive
Arlington, Virginia 22203-1714

Primary Point of Contact.:

Michael C. Fritze,

Program Manager, MTO

DARPA-BAA-10-12@darpa.mil