Growing carbon nanotubes with a well-controlled direction, orientation and size by using faceted catalytic dots to form transistors earned U.S. Patent 7,638,383 for Intel Corporation (Santa Clara, CA). The angled facets of Germanium (Ge) dots allow different sides of the dots to be treated differently. Different sides and the top may be doped with growth inhibitors and growth promoters so that nanotubes may be grown in any desired position and angle. Nanotubes may also be grown in more than one position on a single dot, depending on the desired connections, according to inventors Been-Yih Jin, Robert S. Chau, Brian S. Doyle and Marko Radosavljevic.
Carbon nanotubes (CNT) have been investigated for a wide range of possible applications. However, at present, it remains difficult to control the size of CNT, both in diameter and length. Size is an important factor in the electrical properties as well as the mechanical properties of the device. It is also difficult to control the chirality of a CNT which affect the CNT's transport properties. The placement and orientation of a CNT is also not well controlled. Without a way to reliably and inexpensively control the size, distribution, and growth direction of nanotubes to within a few nanometers, their applications are limited.
One such application is in making discrete CNT transistors. Prototype transistors have been shown to exhibit a variety of promising transport properties. Field effect transistors (FET) made with CNTs have shown very high thermal conductivity, high current conduction, and very high gain compared with silicon devices. However, these prototypes cannot yet be manufactured with the cost, precision, and reliability of conventional technologies, such as mature silicon based CMOS (complementary metal oxide semiconductor) technology.
According to the Intel inventors, carbon nanotubes may be grown with precision in size, placement and direction using facets of catalysis-cladded, self-assembled SiGe/Ge dots (silicon-germanium/germanium) to form field effect transistors. The wetting capability of Ge or SiGe alloys (Ostwald ripening) may be used to carry and self assemble a thin catalytic capping layer on the dots. The capping layer then forms pyramidal catalytic islands. Growth inhibitor and growth promoter layers may be applied to the catalyst using tilted and twisted low energy high dose implants. Carbon nanotubes may then be grown on the growth promoter sections.
Photolithography and isolation may then be used to define the positions of the catalytic islands as well as their size and orientation. Photolithography, printing and other techniques may then be used to define source, drain, and isolation areas.
This self assembling property of materials, such as the low melting point group IV materials (Ge or Si1-xGex alloys) may be used to form faceted catalytic dots with facets aligned to axes of the dots' crystalline structure. This allows catalytical islands to be formed with good control of the size. It also allows facets to be formed on the islands with a defined orientation and self-aligned to the substrate on which they are formed. Angled and tilted growth inhibiting and growth promotion implants on selected facets enable the precise control of the size, position and growth direction of carbon nanotubes.
The drawing figures show in a diagram form a sequence of operations that may be used to grow precisely controlled carbon nanotubes and to form transistors, in this case FETs using the nanotubes. In FIG. 1A, sources and a drain are defined on a silicon substrate. While the described example is in the context of a silicon substrate, a variety of other material may be used with appropriate modifications, such as gallium arsenide, lithium niobate and ceramics.
This self assembling property of materials, such as the low melting point group IV materials (Ge or Si1-xGex alloys) may be used to form faceted catalytic dots with facets aligned to axes of the dots' crystalline structure. This allows catalytical islands to be formed with good control of the size. It also allows facets to be formed on the islands with a defined orientation and self-aligned to the substrate on which they are formed. Angled and tilted growth inhibiting and growth promotion implants on selected facets enable the precise control of the size, position and growth direction of carbon nanotubes.
The drawing figures show in a diagram form a sequence of operations that may be used to grow precisely controlled carbon nanotubes and to form transistors, in this case FETs using the nanotubes. In FIG. 1A, sources and a drain are defined on a silicon substrate. While the described example is in the context of a silicon substrate, a variety of other material may be used with appropriate modifications, such as gallium arsenide, lithium niobate and ceramics.
FIG. 1A is a diagram of a portion of a silicon substrate showing sources and a drain according to an embodiment of the invention;
FIG. 1B is a diagram of a portion of a silicon substrate showing sources and a drain
FIG. 1B is a diagram of a portion of a silicon substrate showing sources and a drain
FIG. 2 is a diagram of the portion of the silicon substrate showing the source and drain masked off
FIG. 3 is a diagram of the portion of the silicon substrate showing a deposited wetting layer according to an embodiment of the invention;
FIG. 4 is a diagram of the portion of the silicon substrate showing a deposited catalytic layer according to an embodiment of the invention;
FIG. 5 is a diagram of the portion of the silicon substrate showing a pyramidal dot after annealing
FIG. 6 is a diagram of the portion of the silicon substrate showing the pyramidal dot with masking and catalytic layers
FIG. 6 is a diagram of the portion of the silicon substrate showing the pyramidal dot with masking and catalytic layers
FIG. 7 is a more detailed cross-sectional diagram of the pyramidal dot of FIG. 6
FIG. 8A is a top elevation diagram of a grouping of pyramidal dots aligned with the crystalline structure of the wafer
FIG. 8B is close-up of a portion of the top elevation diagram of FIG. 8A;
FIG. 9 is a diagram of the portion of the silicon substrate showing doping with a growth promotion agent
FIG. 10 is a diagram of the portion of the silicon substrate showing doping with a growth inhibiting agent
FIG. 11 is a diagram of the portion of the silicon substrate showing the growth of nanotubes
FIG. 12 is a diagram of the portion of the silicon substrate showing the growth inhibiting doped layer removed
FIG. 13 is a diagram of the portion of the silicon substrate showing deposited gate dielectric
FIG. 14 is a diagram of the portion of the silicon substrate showing gate electrodes formed
FIG. 14 is a diagram of the portion of the silicon substrate showing gate electrodes formed
FIG. 15 is a diagram of the portion of the silicon substrate showing source and drain contacts and an ILDO
The self assembling property of materials, such as the low melting point group IV materials (Ge or Si1-xGex alloys) may be used to form faceted catalytic dots with facets aligned to axes of the dots' crystalline structure. This allows catalytical islands to be formed with good control of the size. It also allows facets to be formed on the islands with a defined orientation and self-aligned to the substrate on which they are formed. Angled and tilted growth inhibiting and growth promotion implants on selected facets enable the precise control of the size, position and growth direction of carbon nanotubes.
Nanotubes are grown, using, for example CVD (Chemical Vapor Deposition) on the substrate. Due to the doping, the nanotubes grow only on the selected facet, that is, on the surfaces that have no growth inhibiting dopant and that do have a growth promoting dopant. Nanotubes may also be grown on surfaces that have no dopant or at different rates on different surfaces depending on whether there is a growth promoting dopant, growth inhibiting dopant or no dopant at all.
