Foster Miller, Inc. (Waltham, MA) inventors reveal carbon nanotube-based electronic devices made by electrolytic deposition and their applications in U.S. Patent 7,632,762. Thomas Tiano, John Gannon, Charles Carey, Brian Farrell, and Richard Czerw developed a novel method of fabricating single-wall carbon nanotube devices that includes the combination of an electrolytic deposition process, followed by an operation to selectively "burn out" the percolated metallic nanotubes and, thereby, form a semiconducting nanotube-based electronic device. The devices that can be formed include chemical or biological sensors, carbon nanotube field-effect transistors (CNFETs), tunnel junctions, Schottky junctions, and multi-dimensional nanotube arrays to give only a few examples.
The invention also provides preferred methods of forming a semiconductive device by applying a bias voltage to a carbon nanotube rope. The plurality of metallic single-wall carbon nanotubes are removed (e.g., by application of bias voltage) in an amount sufficient to form the semiconducting device. The Foster-Wheeler fabrication method provides an efficient, cost-effective process for mass producing nanotube-based electronic devices that is scalable.
SWNT ropes or single nanotubes can be used to make junctions, by the insertion of a layer of suitable material between the nanotubes. Additionally, a molecular wrap or an insulating layer that is about 10 nm thick forms a tunnel junction. There are many types of devices standard in the microelectronic art that are formed from tunnel junctions. The simplest tunnel junction application is as a two-state logic device that has a low conductivity state at low voltage and a high conductivity state above a voltage threshold level. A high quality oxide layer may be used to implement an FET, within which a voltage on one nanotube depletes or injects electrons into the other nanotube. One nanotube, in this case, is a semiconducting or burnt-out SWNT rope, while the other is a metallic nanotube or SWNT rope that has percolating metallic paths.
Very dense arrays of junctions may be made by use of crossover nanotube junctions, such as crossover nanotube junctions of 2D nanotube array or crossover nanotube junctions of 2D nanotube array. These arrays use the .about.1 micron length nanotubes, in order to interface with control, i.e., input and output lines that are formed by conventional lithography. A crossbar geometry is used to define junctions on a submicron (50 nm) scale.
A laser-patterned template enables self-cleaning surfaces to be grown over large areas at lower cost than is possible using lithographic methods, according to A*Star researchers. The surfaces mimic the hydrophobic qualities of the lotus plant as well as its self cleaning qualities.
Fig. 1: Etching a dense array of pits into the surface of a silicon substrate with a laser increases its water repellency. Using this surface as a template to imprint the reverse of this pattern into a sol–gel film results in a surface that is even more water repellent.
The leaves of the lotus flower have a remarkable property—they are self-cleaning. Because the leaves are hydrophobic, or water repellent, water that comes into contact with them forms spherical beads that roll along the leaf picking up dust and dirt on from its surface. Now, a research group from the Singapore Institute of Manufacturing Technology of A*STAR have developed a method that could eventually enable large surface areas to be coated with a hydrophobic layer that mimics this self-cleaning property1.
The lotus plant has given its name to a natural self-cleaning mechanism: The extremely water-repellent (superhydrophobic) surface of its leaves causes drops of water to form spheres, which roll off the leaf, sweeping any dirt away. The lotus leaf is equipped with 3 to 10 µm “bumps” that are in turn coated with a nanoscopic water-repellent coating.
“Hydrophobic surfaces are desirable for many industrial applications such as anti-biofouling paints for boats, anti-sticking of snow for antennas and windows, self-cleaning windshields for automobiles, stain-resistant textiles and anti-soiling architectural coatings,” explains Xincai Wang from the group. Many techniques exist for making a surface hydrophobic. Coating a surface with chemicals that are naturally water repellent, for example, is one approach.
However, this may not work for many surfaces. Moreover, such chemicals gradually degrade and are easily rubbed off, requiring continual retreatment. A more robust and longer-lasting approach is to change the microscopic structure of a surface. It is well known that structuring a surface to have micrometer-sized protrusions increases its water-repelling properties. But conventional techniques for patterning these structures, such as photolithography combined with reactive ion etching, are time-consuming and expensive.
The technique developed by Wang and co-workers produces hydrophobic surfaces that are robust and potentially much cheaper than those produced by photolithgraphic patterning. First, the researchers drilled a dense array of pits into a flat silicon substrate with a sharply focused, ultraviolet laser (Fig. 1). They found that this step on its own increased the hydrophobicity of the surface, causing water droplets on its surface to form a more spherical shape than on an untreated surface. Such behavior is typically quantified by measuring the angle made by the base of a droplet with the surface, known as the wetting angle, which in this case increased from 64.2° to 97.5°.
Next, Wang and co-workers used the silicon surface as a stamp to imprint the inverse of its pattern into the surface of a soft sol–gel film. Without modification, these films exhibited hydrophibicity with a contact angle of 110°. But imprinting them with the silicon stamp increased this to 138°. In future work, the researchers intend to extend this approach to make hydrophobic surfaces over large areas on an industrial scale.
Wang, X.C., Wu, L.Y.L., Shao, Q. & Zheng, H.Y. Laser micro structuring on a Si substrate for improving surface hydrophobicity. Journal of Micromechanics and Microengineering19, 085025 (2009). | article
STMicroelectronics (ST), a leading semiconductor manufacturer, has selected Applied Materials’ high-k/metal gate (HKMG) technology for the production of its 28nm logic devices. Applied’s state-of-the-art HKMG technology will be used to fabricate the critical transistor gate layers in ST’s next-generation system-on-chip devices at its facility in Crolles, France.
HKMG is an emerging technology that allows the continuation of Moore’s Law, enabling faster switching speed while reducing device power consumption. Replacing traditional silicon dioxide as the main gate dielectric, the new HKMG structure integrates a hafnium-based high-k material with a new metal gate electrode to increase capacitance and control leakage current.
“We are impressed and extremely pleased with the speed at which Applied has developed integrated high-k/metal gate solutions that address our 28nm device requirements,” said Joël Hartmann, Silicon Technology Development Director for STMicroelectronics in Crolles, France. “We are confident that through our continued collaboration with Applied Materials we can quickly bring our 28nm HKMG solution into volume production."
Major challenges to implementing HKMG technology for the industry have been the development of manufacturable processes using new materials that can provide optimum transistor characteristics while maintaining the integrity of the dielectric stack. Applied has developed a multi-step process combining its leading-edge technologies to provide ST with a robust and reliable HKMG solution. For more information on Applied’s HKMG technology, visit:
“This important collaboration with ST demonstrates that our high-k/metal gate solution can be successfully integrated in their logic devices with superior performance,” said Steve Ghanayem, Corporate Vice President and General Manager of Applied’s Front End and Metal Deposition Products business unit. “ST’s selection of our high-k/metal gate processes is a strong testament to the work we’ve done to provide production-worthy solutions for this challenging new transistor technology.”
ASML (Veldhoven, the Netherlands) along with its subsidiary Brion Technologies, have announced a broad-scoped joint development project with STMicroelectronics (ST) to accelerate 28-nm node deployment and 22-nm node development.
This joint development project, code-named SOLID (Silicon printing Optimization with Lithography control and Integrated Design), seeks to optimize the patterning process from design to manufacturing, extend characterization tools and methods to develop new correction/compensation techniques for reducing variability and explore breakthrough lithography solutions for manufacturing complex chips at sub-30-nm nodes.
ST will work with TachyonTM SMO source-mask co-optimization in tandem with ASML's advanced illumination sources, including the recently announced FlexRayTM programmable illuminator. Together Tachyon SMO and FlexRay will provide ST faster development cycles in R&D and faster ramp to production. Till now, ST has successfully used Brion's Tachyon OPC+ optical proximity correction and LMC lithography manufacturability check in its 45-nm production.
"This joint development project combined with ASML's integrated suite of lithography products, including Brion computational solutions and the latest generation of TWINSCAN NXT scanner provides ST with computational and wafer lithography technologies that will enable us to develop optimum manufacturing solutions at 28-nm and below," said Joël Hartmann, Silicon Technology Development Director for STMicroelectronics, at Crolles, France. "Furthermore this ST-ASML effort is a reinforcement of the Crolles cooperative R&D cluster, which gathers partners around the development and enabling of low-power SoC (System on Chip) and value-added application-specific technologies. This is a perfect example of a project developed within the framework of the Nano2012 program."
The Nano 2012 program is a cooperation between IBM Fishkill and Albany (NY State), STMicroelectronics and CEA-LETI and focuses on nanoelectronics which aims to boost the technological lead and competitive position of the Grenoble area in the changing conditions of the global semiconductor industry and consolidate its leadership position in the development of (32 and 22 nm) CMOS technologies and derivative technologies for system-on-chips (embedded memory, analog/RF devices, etc.). Over the next five years Nano 2012 will be allocated a $3.3 billion (€2.3B) R&D budget with a further $1.82 billion (€1.25B) for capital investment, making it one of France’s biggest industrial projects. National and local government are providing substantial support for the project, contributing some $667 million (€457M). Realization of this project will make Grenoble- Isere a global centre for tomorrow’s nanoelectronics, with potential for creating about 650 jobs in the Grenoble area. In just 10 years more than $8.7 billion (€6B) will have been invested in micro and nano-electronics in Grenoble-Isere.
Lawrence Berkeley National Laboratory scientist Alex Zettl and his team have developed a simple and efficient way to obtain freestanding graphene membranes that can be used to generate etch masks and doping patterns for microelectronic devices. The researchers have used electron-beam induced deposition (EBID) to deposit amorphous carbon on these membranes to obtain arbitrary patterns with a nanometer-scale resolution. In the case of a periodic grating, they have obtained a half-pitch of 2.5 nm. The technology is available for licensing under the title, "Graphene Membranes for Nanometer-scale Lithography and Single Atom Resolution TEM Imaging."
On a bulk substrate, the spatial resolution of EBID and conventional lithography is limited by scattered and secondary electrons, with a minimum half pitch of around 20 nm. Although good resolution has been achieved by EBID on ultrathin amorphous carbon and silicon nitride membranes, for many applications graphene is a preferable material; it has interesting electronic properties that can be altered by doping, shaping, or defect generation. By using graphene membranes, Berkeley Lab researchers directly pattern the material that is likely to be used in a host of next generation electronic devices.
The single-atom thickness Berkeley Lab membranes also can be used in a TEM to visualize defects, vacancies, carbon chains, individual carbon adatoms and their dynamics. In addition, they are promising as TEM support structures for imaging other materials because they provide a highly transparent, crystalline background. (See the publication below for a detailed description of imaging achievements using these membranes.)
The contiguous size of one of the Berkeley Lab sheets is on the order of 50 microns. These could be made into a mosaic of a larger size but large contiguous sheets are not necessary, as one 50 micron sheet covers several grid holes. The Berkeley Lab foil is exceptionally robust. One can prepare and store it in air, and it withstands mechanical shock and is fairly immune to electrostatic discharge. It is also easy to clean and no special handling precautions are needed.
APPLICATIONS OF TECHNOLOGY:
Using electron-beam induced deposition (EBID) on graphene membranes to create nano-scale
doping patterns for electronic circuits
lithography etch masks
diffraction gratings (for monochromators, spectrometers, wavelength division multiplexing devices, optical pulse compressing devices and other optical devices)
Investigating the properties of graphene and the dynamics or structure of adsorbed molecules
Support structures for TEM imaging to investigating the properties of other materials
Chemical Detection
ADVANTAGES:
Direct-write deposition of arbitrary patterns with a demonstrated resolution of 2.5 nm
Two orders of magnitude thinner than previously studied membranes, reducing the effect of secondary and scattered electrons (no deposits outside intended structures)
Membranes are robust, air and shock tolerant, fairly immune to electrostatic discharge, and easy to clean
A wide range of materials other than carbon can be deposited
Single-atom resolution can be achieved for imaging applications
Nanoscale lithographic apparatus are indispensible tools used to manufacture integrated circuits (ICs), flat panel displays, optoelectronic, sensors, microfluidic devices and photonic devices including solar power cells as well as micro-electromechanical systems (MEMS), all involving nanoscale structures. The advancement in photolithography technology has been the key to the rapid development of the semiconductor industry. Countless innovations and progress in this field will continue to drive technological development in the semiconductor industry. Nanofabrication equipment has been used to create integrated circuits in the 65nm to 45nm range, and companies are now moving to manufacturing computer chips and memory chips in the 32nm range.
According to a recently published report from iRAP, Inc., ET-110 Nanolithography Equipment for IT, Electronics and Photonics – A Technology, Industry and Global Market Analysis, the overall market for wafers, materials and nanofabrication equipment is expected to grow at 11% a year for the next five years, from an estimated $65.8 billion in 2009 to $111 billion in 2014.
In 2008, nanofabrication apparatus enabled semiconductor manufacturers to transform more than $11.4 billion worth of silicon wafer material into more than $425 billion worth of semiconductor, photonic, opto-electonic and MEMS material devices for use in computers and electronic devices, which in turn constituted a global market valued in excess of $1.38 trillion dollars, plus related services valued at $5 trillion dollars globally. Semiconductor and electronics manufacturers spent roughly $80 billion in 2007 and $74 billion in 2008 for silicon wafers, materials and equipment which allowed them to manufacture integrated circuits at scales to 45nm, and they are now beginning to buy equipment to manufacture integrated circuits at the scales of 32nm and 22nm.
The equipment for deposition of materials onto silicon wafers represented 19% of the nanofabrication market and was valued at $11.4 billion for 2008. Lithographic equipment was 20% of the market, valued at $12.4 billion. Beam technology and light sources associated with lithography and semiconductors represented 9% of the market and were valued at $5.594 billion. Testing of semiconductor components and processes represented 17% of the nanofabrication market with a value of $10.56 billion. Metrology was 11% of the 2008 market, with a value of $6.83 billion. Other processes were 6% of the 2008 market, with a value of $3.730 billion.
Companies involved in nanofabrication materials, apparatus, metrology and testing for the IT and electronics industry had sales in excess of $80 billion in 2007 and more than $73.5 billion in 2008, reflecting the worldwide economic downturn. Research and development (R&D) spending for improved nanofabrication techniques and equipment exceeds $7 billion a year at the corporate level. Research and development of manufacturing equipment for 45nm technology for semiconductors, which began in 2003, is now the manufacturing standard, and the new standard under development is 32nm architecture, beginning to be implemented in 2009. Each reduction in size results in more powerful microprocessors, memory chips and silicon-based solar power collectors, in which creates new demands. Lithography, including masks and resist, and associated metrology currently comprises 30% to 40% of the entire cost of semiconductor manufacturing. This fraction depends strongly on the product mix, volume of integrated circuits in demand per design, and age of equipment in the factory.
Market Value of Nanofabrication Equipment, Materials and Wafers for Semiconductors, Electronics and Photonics through 2014
Source: iRAP, Inc.
Share of Nanofabrication Equipment, Materials and Wafers for Semiconductors, 2009-2014
Source: iRAP, Inc
More details of the report are available from Innovative Research and Products (iRAP), Inc., visit www.innoresearch.net or contact iRAP at 203-569-790; or email at:
Data and analysis extracted from this press release must be accompanied by a statement identifyingiRAP, Inc., P.O. Box 16760, Stamford, CT 06905, USA, Telephone: (203) 569-7909, Email: marketing@innoresearch.net as the source and publisher, along with report number, which can be found in the first paragraph of this release.
IBM has earned U. S. Patent 7,628,974 for its method to control single wall carbon nanotube (SWNT) diameter growth during manufacturing by either chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
Carbon nanotube based field effect transistors (CNTFETs) show great promise for device applications. Recently CNTFETs with excellent electrical characteristics comparable to state-of-the-art silicon MOSFETs have been demonstrated. The electrical characteristics of CNTFETs however depends largely on the band-gap of the single wall carbon nanotube (SWNT) forming the channel of the transistor. Since the band-gap of SWNTs has a strong dependence on the diameter, accurate control of the diameter is essential to the success of any device technology based on carbon nanotubes.
A crucial difficulty in obtaining individual SWNTs by CVD is control of nanometric catalyst particle size at growth temperatures of 700-1000.degree. C. It has been theorized that the particle size of the growth catalyst used can define the diameter of as grown carbon nanotubes. This hypothesis has been supported by the observation that catalytic particles at the ends of CVD grown SWNT have sizes commensurate with the nanotube diameters Catalysts typically employed are transition metals, notably Fe, Mo, Co, NI, Ti, Cr, Ru, W, Mn, Re, Rh, Pd, V or alloys thereof. However, the synthesis of small catalyst particles with a narrow diameter distribution is complicated and difficult to control.
IBM controls the diameter of CVD or PECVD grown CNTs based on the control of the residence time of the gases in the reactor such as by controlling the pressure, or the gas flow rates, or a combination of both, independent of catalyst particle size, according to inventors Alfred Grill, Deborah Neumayer and Dinkar Singh.
The gas residence time is a measure of the average time of the gas in the reactor. Thus, if the flow is constant and the pressure increases, the residence time increases, and if the pressure is constant and the flow increases the residence time decreases. The inventors unexpectedly discovered that by varying the residence they can influence the nanotube diameter. If the residence time is too high, only pyrolytic carbon is deposited and if the residence time is too low, nothing is deposited. The residence time is typically about 1 minute to about 20 minutes and more typically about 1 to about 10 minutes. The residence time is typically determined by controlling the pressure, flow or both the pressure and flow in the reactor. By varying the residence time (e.g growth pressure and/or flow rates) of the CNT precursor gases in the CVD or PECVD reactor, nanotube diameter can be varied from about 0.2 nanometers to several nanometers to 100 nanometers.
FIGS. 1A-1B show scanning electron microscope images of CNTs grown at atmospheric pressure using identical catalysts, but different gas flows. (FIG. 1A shows that higher gas flow results in relatively thin tubes, while FIG. 1B shows that lower gas flows in result in relatively thick tubes).
A further aspect of the patent relates to fabricating a SWNT or array of SWNTs having well defined diameters and origins by the above disclosed processes wherein the SWNTs form the channel of a field effect transistor. A field-effect transistor having source and drain regions and a channel located between the source and drain regions is obtained by a process comprising: a) depositing a thin film of catalyst; b) lithographically patterning the thin film of catalyst to provide catalyst only in the source or drain region or both; c) removing unwanted catalyst from the channel region defined by the lithographic pattern; and d) growing nanotube with a well controlled diameter ranging from about 0.2 nanometers to about 100 nanometers by controlling the residence time of gases in the reactor used for the growing of the nanotube and wherein the channel region extends from the source region to the drain region.
ASML Netherlands B.V. (Veldhoven, NL) inventor Oscar Franciscus Jozephus Noordman discloses a system for controlling the energy of laser radiation pulses used in semiconductor fabrication in U.S. Patent 7,626,182. A detector monitors energy of the pulses and an optical shutter trims the radiation pulses after a suitable optical delay line. The accuracy of the control of the energy of the radiation pulses can be improved by matching a rate of response of the radiation detector to a rate of response of the optical shutter. The excimer laser provides a radiation source generating pulses of radiation that have consistent energy levels. In addition, the radiation pulse energy control system can be used as part of a lithographic apparatus. For example, the radiation pulse energy control system can be configured to adjust the energy of the pulses of radiation that are input to, or output from, the illuminator.
According to U.S. Patent 7,626,182 , applications include the manufacture of integrated circuits, integrated optical systems, guidance and detection patterns for magnetic domain memories, flat-panel displays, liquid-crystal displays (LCDs), thin-film magnetic heads, micro-electromechanical devices (MEMS), light emitting diodes (LEDs), etc. Also, for instance in a flat panel display, the laser can be used to assist in the creation of a variety of layers, e.g. a thin film transistor layer and/or a color filter layer.
The laser can be used in optical lithography as well as in imprint lithography. In imprint lithography a topography in a patterning device defines the pattern created on a substrate. The topography of the patterning device can be pressed into a layer of resist supplied to the substrate whereupon the resist is cured by applying electromagnetic radiation, heat, pressure or a combination thereof. The patterning device is moved out of the resist leaving a pattern in it after the resist is cured.
Hewlett-Packard Company inventors Zhiyong Li and R. Stanley developed nanoimprint lithography methods to manufacture photonic devices and nano-structures which are detailed in U.S. Patent Application 20090274874. The photonic device includes a substrate and at least one molecularly assembled or atomic layer deposited nano-structure defined on the substrate. The nano-structure has a controlled resolution from 100 nanometers to 10 nanometers or smaller. HP nanoimprint lithography may be used to manufacture photonic devices, nanoelectronic devices, nanoplasmonic devices, or enhanced Raman spectroscopy devices.
Nano-imprint lithography was initiated as a process to achieve nanoscale features (about 100 nm or smaller) with high throughput and relatively low cost in structures such as molecular electronic devices. During many imprinting processes, the nanoscale features are transferred from a mold to a polymer layer. As non-limiting examples, the mold may be used for a thermal imprint process, as well as for a UV-based imprint process.
In the thermal imprint process, to deform the shape of the polymer, the temperature of the film and mold is generally higher than the glass transition temperature of the polymer, so that the polymer flows more easily to conform to the shape of the mold. Hydrostatic pressure may be used to press the mold into the polymer film, thus forming a replica of the mold in the polymer layer. The press is then cooled below the glass transition temperature to "freeze" the polymer and form a more rigid copy of the features in the mold. The mold is then removed from the substrate.
In the alternate UV imprint process, a UV-curable monomer solution is used instead of a thermoplastic polymer. The monomer layer is formed between the mold and the substrate. When exposed to a UV light, the monomer layer is polymerized to form a film with the desired patterns thereon.
Embodiments of the method advantageously enable control over the formation and resolution of nano-structures at or below 100 nm. Without being bound to any theory, it is believed that the removal of a polymeric resist from the process advantageously contributes to the ability to control the resolution on the sub-100 nm scale. The use of polymeric resists during nano-imprinting may deleteriously affect feature resolution at or below 100 nm (especially at or below 10 nm), in part, because of the proximity effect from the scattering of electrons or ions in the polymeric resist (e.g., during electron beam (e-beam) lithography).
In some instances, the desirable critical dimension (e.g., at or below 10 nm or at or below 30 nm) of the nanostructure is comparable with the molecule size of the polymeric resist, as such, it may be difficult to achieve uniformity and resolution at the critical dimension. It is further believed that the mechanical strength of polymer resists prevents the formation of a nanoscale pattern with a desirable aspect ratio that is capable of surviving liftoff or etching processes. Still further, techniques such as e-beam lithography, UV lithography, or X-ray lithography may result in significant edge roughness on the patterned polymeric resist, which may be problematic when the patterned features are at or below 30 nm. The method(s) utilize guided molecular assembly or atomic layer deposition, both of which eliminate the use of polymeric resists and enhance feature precision control.
FIG. 1 depicts an embodiment of the method for forming nano-structures. Generally, the method includes establishing a mold having nano-features in contact with a substrate, thereby forming at least one of a channel or a semi-channel, wherein the channel and/or semi-channel is defined at least by an exposed surface of the substrate, an exposed surface of the mold, and a side surface of an adjacent nano-feature of the mold, the nano-features of the mold having a releasing material established thereon, as shown at reference numeral 100; exposing the channel and/or semi-channel to vapor phase assembly or atomic layer deposition to form a layer having a predetermined thickness within the channel, as shown at reference numeral 102; and releasing the mold from the substrate, as shown at reference numeral 104.
The method shown in FIG. 1 is further described in reference to FIGS. 2A through 2F. More specifically, FIGS. 2A through 2D together depict one embodiment of the method for forming the nano-structures, and FIGS. 2A through 2C, 2E and 2F together depict another embodiment of the method for forming the nano-structures. As such, FIG. 2D depicts one embodiment of the resulting structure 10, and FIG. 2F depicts another embodiment of the resulting structure 10'. Such structures 10, 10' may advantageously be used as or in photonic devices, nanoelectronic devices, nanoplasmonic devices, or enhanced Raman spectroscopy devices.
Centre National De La Recherche Scientifique (C.N.R.S.) (Paris, FR) and Universitat De Valencia (Valencia, ES) investigators developed a new process for the application of thin layers of substantially pure spin transition molecular materials while maintaining the hysteresis properties of the material. The process makes it possible to obtain a dense uniform surface with very low roughness. By "thin layer" deposition is meant the application onto a silicon substrate of a layer of material whose thickness lies between 1 nm and 10 micrometers.
According to inventors Azzedine Bousseksou (Toulouse, FR); Gabor Molnar (Toulouse, FR), Saioa Cobo (Castanet Tolosan, FR), Lionel Salmon (Carcassonne, FR), Jose Antonio Real Cabezos (Valencia, ES) and Christophe Vieu (Auzeville Tolosane, FR), there is at the present time no other method through which a thin layer of spin transition complexes can be deposited as a thin layer while maintaining the properties of spin transition, hysteresis and a surface condition of acceptable quality. It is therefore particularly desirable to provide a process for the deposition of spin transition complexes as thin layers which will fulfill these requirements.
The research team discovered a new process of thin layer application which fulfils these requirements. In particular the process makes it possible to maintain properties such as the hysteresis, transition temperature, etc., of the massive material when it is deposited as a thin layer. In addition to this the thin layer comprises only the spin transition compound, so it is not necessary to use a mixture, as is the case in spin coating, where a binding polymer/material mixture is required
The process, detailed in U.S. Patent Application 20090291328, also makes it possible to control the thickness of the deposited layers over a very wide range--from a few nanometers to a few micrometers. Furthermore the thin layers obtained are dense, uniform, of very small roughness, generally between 1 and 20 nm. Finally, micro- and nano-structuring of the deposits is possible. The process makes it possible to produce perfectly localized deposits.
The inventors have prepared a bistable thin layer comprising a substantially pure spin transition material for the first time. This layer can be subsequently micro/nano-structured. .
The substrate may be micro- or nano-structured, using conventional techniques. Micro- or nano-structures of thin layers of spin transition compounds may be manufactured using a microtechnology technique known as "lift-off". One important condition for the use of this process is that the thin layer should be insoluble in the solvent used to lift the resin (for example acetone). This condition is fulfilled by three-dimensional systems, in particular those described below, which are very poorly soluble in common solvents. In the case of deposits made using the layer-by-layer technique an additional condition must be fulfilled--the resin used to mask the surface must be insoluble in the solvent used for deposition. This problem does not arise in the case of the process of deposition by evaporation.
In order to manufacture micro/nano-structured molecular deposits the substrate is first coated with a photosensitive resin and then different resin patterns are obtained by standard photolithography or electronic lithography. The spin transition compound is then deposited layer-by-layer or by thermal evaporation. In the last (lift-off) step the patterns of resin (negative image) are dissolved in acetone, leaving patterns comprising the molecular complex (positive image) which are insoluble in acetone on the substrate.
This method makes it possible to deposit the compound as small elements of controlled size (of micron and nanometer dimensions) having a very favorable morphology (dense with little roughness) for various envisaged applications using spin transition molecular compounds.
FIG. 9: Diagrammatical presentation of the process for the microstructuring of thin layers of the spin transition complex Fe[HB(pz).sub.3].sub.2 by photolithography and thermal evaporation.
FIG. 10: Photographs of microstructures of the compound Fe[(HB(pz).sub.3].sub.2. The metal areas not coated with the product correspond to areas protected by the photolithographic resin.
FIG. 11: Diagrammatical presentation of the process for microstructuring thin layers of the spin transition complex Fe(pyrazine)[Pt(CN).sub.4] by electronic lithography and layer-by-layer deposition and lift-off.
FIG. 12: Images obtained by SEM of a layer according to the invention having different structures obtained following fifteen deposition cycles (a, b: 2 .mu.m; c: 500 nm; d, e: 200 nm; f: 30 nm). The bars on the scale are 30 .mu.m (a), 5 .mu.m (b, c, d) and 500 nm (e, f) respectively.
The figure portrays how $85 billion in equipment and materials purchased by semiconductor and microelectronic manufacturers in 2007 supported more than $6.3 trillion dollars in worldwide economic activity made possible through the production of semiconductor computer chips with transistors manufactured at nanoscales since 2001. Equipment for fabricating millions of nanosized transistors in silicon chips which enable modern computers, communications and are found in all modern automobiles, aviation and aerospace equipment. Source: DraftENIAC Multi-Annual Strategic Plan and Research Agenda 2010 (MASP) proposed by the Aeneas (Association of European Nanoelectronics Activities).
Micro/Nanoelectronics have become integral to life and work – and the trend is ever upward. One "Grand Challenge" identified in the Strategic Plan is the development of extreme ultraviolate (EUV) lithography and complementary 1Xnm patterning as a chip mass manufacturing technology of the next decade.
Technology: Extreme Ultra-Violet (EUV) lithography is anticipated to become the key enabler for More Moore chip mass manufacturing beginning at 22nm feature sizes (half-pitch). Major technology solutions need to be developed: a high throughput EUV machine including e.g. high-power EUV sources and optics for high quality imaging at 13.5nm wavelength; EUV infrastructure and metrology including mask fabrication processes, cleaning, inspection and review tools, sensitive resists, defect engineering and process control. Furthermore, the development of complementary 1Xnm patterning technologies as e.g. e-beam lithography is required for mask making, fast prototyping and low-volume manufacturing.
Commercial Market: EUV lithography addresses a large market with an estimated annual market of $4.5 billion (€3 billion) in 2015. European upfront investments in EUV lithography exceeds $1.5 (€1) billion . The substantial markets for the EUV infrastructure and complementary 1Xnm patterning technologies are additional. It is important to note that Europe’s leading role achieved in the 193nm immersion lithography can only be sustained by a successful introduction of EUV lithography, states the Strategic Plan.
EU Funding Rationale: The high risk in the huge upfront investment and the long-term vision of re-establishing EUV lithography and infrastructure require public funding to realize the multi-billion dollar market potential over the next decade. Furthermore,ENIAC funding will allow Europe to gain in-depth knowledge of leading edge semiconductor manufacturing all over the world and to create and sustained employment of highly qualified individuals in Europe.
ENIAC: The development of EUV lithography and infrastructure, as well as, the complementary 1Xnm patterning technologies are highly involved tasks that require competencies and focused collaboration of large firms, SMEs and institutes from several European countries. ENIAC brings all these entities together in a collaborative $4.5 billion research project that will function through the 2009-2013 time period.
The market for EUV technology, lithography and nanofabrication equipment for the semiconductor, photonic, sensor and MEMS industries is the subject of upcoming report "NANOFABRICATION EQUIPMENT FOR INFORMATION TECHNOLOGY AND ELECTRONICS, A GLOBAL INDUSTRY AND MARKET ANALYSIS"" from Innovative Research and Products Inc.
